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Visitor
Visitor
7,670 Views
Registered: ‎09-20-2007

Sysgen Fir Compiler block in fixed fractional rate mode

I'd like to use Sysgen's Fir Compiler Block in the fixed fractional rate mode.
Currently Sysgen (9.1) supports only integer upsample or downsample modes.
Is there any plan to support fixed fractional rate mode in the upcomming releases of Sysgen?
 
Is it possible to generate Fir with the fractional rate in CoreGen and then simulate it in Sysgen as a HDL blackbox?
What should I do to include generated core into the Sysgen model?
 
 
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Xilinx Employee
Xilinx Employee
7,656 Views
Registered: ‎08-07-2007

To submit a formal request to add support for this feature you should open a webcase with Xilinx technical support here:
http://www.xilinx.com/support/clearexpress/websupport.htm

There's no technical reason that you could not use an HDL black box to bring in a FIR Compiler from Core Generator which uses a fixed fractional rate change as long as all the rates involved in the model can be derived from integer multiples of the system period.
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