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Visitor
Visitor
3,692 Views
Registered: ‎06-12-2012

System Gen Shared Memory data transaction speed

Dear Friends,
I have a simple model in SysGen which communicate with PC in HW -JTAG- cosimulation. I want to know the maximum speed and data bandwidth value that HW could transfer.
This simple model is a 8-bits counter and a shared memory for free-running HW cosimulation in 100MHz clock.I want read the counter in simulink.I know it's gonna be a huge data to transfer,but i want read it in burst mode and n successive period , so i picked up shared FIFO with depth of n period.I followed the frame based HW cosimulation examples unfortunately i could not read successive periods of counter even while use semaphore for From FIFO and TO FIFO.
Could you please help me solve this problem.

Regards,
Yas

 

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Xilinx Employee
Xilinx Employee
3,686 Views
Registered: ‎08-02-2011

Hi Yas,

 

You said:

"i could not read successive periods of counter"

 


Can you elaborate on that? What exactly are you seeing?

 

Have you put the HWC block in free-run mode?

www.xilinx.com
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Visitor
Visitor
3,678 Views
Registered: ‎06-12-2012

Dear bwiec,
tnx for ur quick reply and sorry if i could not elaborate my points.
At first, i used the frame based HW cosim example in free running mode.
pic#1 shows simulation result and everything is ok.

 

1.png

 

pic#2 shows HW cosim result and FIFO output goes wrong while FIFO is Full because counter output is not synchronized with "TO FIFO" block's WE pin.

 

2.png

 

pic#3 shows simulation result when i used handshak signal in order to control Full and Empty of shared FIFO. in this case, FIFO WE is active until the FIFO will be full, after that RE is enabled till Empty be issued and so on.

 

3.png

 

pic#4 shows the HW cosim result in Free running and output data is not regular.

 

4.png

am i right?
It seems in Shared FIFO there is no need to synchronization because both "To FIFO" block in HW and "From FIFO" block in HW Cosimulation are the same and actually shared FIFO is usefule for in free running HW cosimulation. HW clocked by it's own and cosimulation blocks run at simulink clock.I'm a bit lost what's wrong?
I'd just like see a counter in HW cosimulation in regular from zero to say 512 and that's important for me.
Suppose we have FFT block which is running in FPGA and we would like to plot FFT result output in simulink scope via HW cosimulation and we should synchronize FFT output with xk_index in order to plot well.

 

Again,thank you so much for your attention,
Yas

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Visitor
Visitor
3,664 Views
Registered: ‎06-12-2012

Hi,

Could anyone help and give me a sysgen model that HW cosimulate a FFT block running in FPGA and plot FFT result in simulink?

 

Thanks all,

Yas

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Anonymous
Not applicable
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HI yayas2,
Hope that you are fine, I have the same problem I want to synchronize a simple counter of 8 bits between hardware and software using FIFO free running hw cosimulation.
Have you fin any solution
Thank you
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