UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor phongduong
Visitor
4,454 Views
Registered: ‎07-19-2008

System Generator 11.3 Hardware-co-simulation Timing Constraint error

Hi,

 

I'm using Spartan 3E Starter Kit Board, and now I want to make simulation using Hardware Co-simulation, but after XFLOW run, it showed that there was 1 timing constraint not met.

 

I have done some search before making this post. Although there were some topics about this error before, but I still find it so confusing for me to understand this situation.

 

When I finish my design with model in MATLAB (3 Mult, 2 AddSub and 1 Delay), I create SGBD Builder exactly as Performing Hardware-in-the-Loop PDF file guide. After that, I generate and it show 1 timing constraint not met:

 

----------------------------------------------------------------------------------------------------------


 

  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   


 

                                            |             |    Slack   | Achievable | Errors |    Score   


 

----------------------------------------------------------------------------------------------------------


 

* TS_hwcosim_sys_clk = PERIOD TIMEGRP "hwco | SETUP       |     5.086ns|    14.914ns|       0|           0


 

  sim_sys_clk" 50 MHz HIGH 50%              | HOLD        |    -3.743ns|            |    5420|    11072268


 

----------------------------------------------------------------------------------------------------------


 

  TS_J_TO_U = MAXDELAY FROM TIMEGRP "J_CLK" | SETUP       |    10.315ns|     4.685ns|       0|           0


 

   TO TIMEGRP "U_CLK" 15 ns                 |             |            |            |        |            


 

----------------------------------------------------------------------------------------------------------


 

  TS_clk_70d40e76 = PERIOD TIMEGRP "clk_70d | MINPERIOD   |    18.348ns|     1.652ns|       0|           0


 

  40e76" 20 ns HIGH 50%                     |             |            |            |        |            


 

----------------------------------------------------------------------------------------------------------


 

  NET "jtag_iface/drck1" PERIOD = 30 ns HIG | SETUP       |    22.981ns|     7.019ns|       0|           0


 

  H 50%                                     | HOLD        |     0.974ns|            |       0|           0


 

----------------------------------------------------------------------------------------------------------

 

I thought using hardware co-simulation that means System Generator automatically match Timing Constraint, if it needs to be changed, should I change in file SGBD Builder s3e_starter.ucf in folder \Xilinx\DSP_Tools\nt\sysgen\plugins\compilation\Hardware Co-Simulation\s3e_starterkit?

Message Edited by phongduong on 01-16-2010 11:46 AM
_______________________________________________________________________
there 10 types of people in the world: those who knows binary and those who don't
0 Kudos
2 Replies
3,552 Views
Registered: ‎02-09-2011

Re: System Generator 11.3 Hardware-co-simulation Timing Constraint error

total path delay should be less than clock period (20 ns in this case for Spartan 3E) and thus slck variable shoild not be negative.

 

0 Kudos
Visitor tommpogg
Visitor
3,378 Views
Registered: ‎09-01-2011

Re: System Generator 11.3 Hardware-co-simulation Timing Constraint error

I have got the same problem. Has anyone found a solution?

0 Kudos