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Visitor
Visitor
5,080 Views
Registered: ‎07-30-2009

System Generator: Divider Generator 3.0 Radix2

When trying to simulate (run in Simulink) this generated system generator block gets stuck with this error:

 

HDL simulation model compilation failed.
ERROR:HDLCompiler:841 - "xlisim_xlDivider_Generator_a7260da14c0d33f14ca30e779fb4a950.vhd" Line 34411: Expecting type std_logic for <ce>.
ERROR:HDLCompiler:841 - "xlisim_xlDivider_Generator_a7260da14c0d33f14ca30e779fb4a950.vhd" Line 34412: Expecting type std_logic for <clk>.
ERROR:HDLCompiler:854 - "xlisim_xlDivider_Generator_a7260da14c0d33f14ca30e779fb4a950.vhd" Line 34396: Unit <behavior> ignored due to previous errors.

etc.

Also trying to run it as hardware cosimulation reports errors.

 

I could use High radix and use an extra multiplier because I need both the quotient and the reminder, but this would generate extra hardware and latency, so the Radix2 option would be ideal. Any idea what's going wrong?

 

(running Xilinx tools 11.2 and matlab 2008a)

Message Edited by mjmvaneerd on 07-30-2009 07:36 AM
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Xilinx Employee
Xilinx Employee
5,049 Views
Registered: ‎11-28-2007

After adding Gateway In/Out to the model (see snapshot below). It simulates fine.

 

Cheers,

Jim

 

Cheers,
Jim
ScreenHunter_01 Jul. 31 10.16.gif
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