UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor dmittiga
Visitor
127 Views
Registered: ‎03-08-2019

System Generator vector gateway names not propagated

Jump to solution

Normally, when using a gateway block, the name of the block is translated to the generated code. The input/output name in the interface uses the name given in the Simulink model. However, when using vector gateway blocks, this is not the case. The name given to the vector gateway block is not replicated in the underlying layers under the mask. Instead they are given generic names like "GatewayIn2" and so on. This results in generated code in which the input/output lines become very confusing and often impossible to map!

confusingGateways.JPG

genericGateways.JPG

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
87 Views
Registered: ‎09-18-2018

Re: System Generator vector gateway names not propagated

Jump to solution

Hello @dmittiga ,

This is a known bug in the system generator Vector gateway blocks. This will be fixed in next release of Vivado. 

The problem can be worked around by disabling the library link of the block , then changing the parameters under the mask . Under the mask of the vector gateway block, there will be an array of scalar block, these names are propagated to HDL. These names can be edited to the name of your top level block for now.

However changing the block parameters requires everything to be done again

 

 

 

1 Reply
Xilinx Employee
Xilinx Employee
88 Views
Registered: ‎09-18-2018

Re: System Generator vector gateway names not propagated

Jump to solution

Hello @dmittiga ,

This is a known bug in the system generator Vector gateway blocks. This will be fixed in next release of Vivado. 

The problem can be worked around by disabling the library link of the block , then changing the parameters under the mask . Under the mask of the vector gateway block, there will be an array of scalar block, these names are propagated to HDL. These names can be edited to the name of your top level block for now.

However changing the block parameters requires everything to be done again