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Observer
Observer
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Registered: ‎03-08-2019

System Generator vector gateway names not propagated

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Normally, when using a gateway block, the name of the block is translated to the generated code. The input/output name in the interface uses the name given in the Simulink model. However, when using vector gateway blocks, this is not the case. The name given to the vector gateway block is not replicated in the underlying layers under the mask. Instead they are given generic names like "GatewayIn2" and so on. This results in generated code in which the input/output lines become very confusing and often impossible to map!

confusingGateways.JPG

genericGateways.JPG

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Xilinx Employee
Xilinx Employee
362 Views
Registered: ‎09-18-2018

Hello @dmittiga ,

This is a known bug in the system generator Vector gateway blocks. This will be fixed in next release of Vivado. 

The problem can be worked around by disabling the library link of the block , then changing the parameters under the mask . Under the mask of the vector gateway block, there will be an array of scalar block, these names are propagated to HDL. These names can be edited to the name of your top level block for now.

However changing the block parameters requires everything to be done again

 

 

 

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Xilinx Employee
Xilinx Employee
363 Views
Registered: ‎09-18-2018

Hello @dmittiga ,

This is a known bug in the system generator Vector gateway blocks. This will be fixed in next release of Vivado. 

The problem can be worked around by disabling the library link of the block , then changing the parameters under the mask . Under the mask of the vector gateway block, there will be an array of scalar block, these names are propagated to HDL. These names can be edited to the name of your top level block for now.

However changing the block parameters requires everything to be done again

 

 

 

View solution in original post