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rajeshkhanna
Adventurer
Adventurer
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Registered: ‎08-09-2013

System generator FIFO with data-width conversion

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HI, In vivado the fifo provided are able to change the data width i.e input port 64 bit and output port 16 bit. The FIFO's provided in system generator are not having such options. how to do if we need such convertion. any reason why the option is not given in system generator. Regards, Rajesh khanna
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vkanchan
Xilinx Employee
Xilinx Employee
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Registered: ‎09-18-2018

Hi @rajeshkhanna ,

Currently the FIFO's do not have the facility of setting asymmetric data widths as in Vivado. This is being considered for Sysgen FIFO blocks in the future releases.

However for now, the XPM FIFO template can be used in Vivado to create a asymmetric FIFO and then import it into Sysgen using the "Import HDL" block.

 

 

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vkanchan
Xilinx Employee
Xilinx Employee
517 Views
Registered: ‎09-18-2018

Hi @rajeshkhanna ,

Currently the FIFO's do not have the facility of setting asymmetric data widths as in Vivado. This is being considered for Sysgen FIFO blocks in the future releases.

However for now, the XPM FIFO template can be used in Vivado to create a asymmetric FIFO and then import it into Sysgen using the "Import HDL" block.

 

 

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rajeshkhanna
Adventurer
Adventurer
491 Views
Registered: ‎08-09-2013
HI,
Thanks for the suggestion.I will try the approach.
Regards,
Rajesh khanna
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