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mdjawaidalam

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03-14-2008 10:55 PM

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03-11-2008

Unexpected result in fft core(Fast Fourier Transform 3.2)

I'm using 128 point Fast Fourier Transform 3.2 core in my project,

and using ISE9.1i and ModelsimSE6.1b in windows environment.

I've configured ModelsimSE for SmartModel use and swift interface.

the simulation report i'm getting is as shown in Fig.1 and Fig.2 (attached here) which has following problems.

1. Figure 1 shows the initial stimulus, in this rfd goes high after two clock period irrespective of any input signal.

and then when i apply 'rst' , only after that it function well. busy, edone, done , dv signals are active at the right time.

2. As shown in Figure 2. I'm giving input 'xn_re = 00000001' (all 128 elements) and 'xn_im = 00000000' fixed,

all 128 xk_re and xk_im values are non zero,

while actual values should be

xk_re=128(0000 0000 1000 0000) only for first index, and rest should be zero.

xk_im= 0(0000 0000 0000 0000) for all index.

3. it is giving diffrent results for diffrent frames even when I'm giving same input(when operated one frame after other)

I'm also attaching my project here.

plz help .....

21 Replies

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dinky123

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03-16-2008 10:31 AM

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Hi,

I am also encountering similar problems with this version. There is a statement in the datasheet to input the data after 3 clock cycles of the corresponding index but if I do so then I am getting undefined values for some of the outputs in the first frame of data and then I had to input first sample data with the rising edge of the rfd pin which gives valid outputs but results are wrong as if I input two exactly same frames consecutively, they should give same results in the frequency domain but I am getting different values for the same streams of inputs. I am using the pipelined solution. Please help.

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mdjawaidalam

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03-16-2008 06:43 PM

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Hi,

I think there is some problem in this virsion, i've checked all possible setings, bt it is giving diffrent results for same input.

Or we should contact xilinx for this virsion if there may be some specific resion.

have u checked my codes? i'm using radix-4 burst I/O as i have to save the resources for other modules also.

good luck.

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__LogiCORE Fast Fourier Transform (xFFT) v3.2/patch 1__

Initial Release in ISE 8.1i IP Update 1

__New Features__

- N/A

__Bug Fixes__

- CR 220574: For the Pipelined Streaming I/O architecture, overflow is signaled for frames with no overflow, preceding or following a frame with an overflow (overflow tainting next or previous frame)

- CR 220203: GUI displays incorrect resource estimates for DSP48 count

- CR 220655: For the Pipelined Streamlining I/O architecture, the core dumps incorrect output data after a reset event (SCLR asserted, or new NFFT value latched in). If two reset events occur less than ~40 CLK cycles apart, the second reset might be incomplete and the core might start generating output values (DV = 1) from an incomplete input frame

__Known Issues__

- Large FFT point size generation times. See (Xilinx Answer 21988).

- Placement Issues when targeting a Virtex-II, Virtex-II Pro, or Spartan-3 device. See (Xilinx Answer 20307).

- First frame after multi-cycle reset might be incorrectly marked as valid. See (Xilinx Answer 24436).

- Slice estimate and implementation results are different. See (Xilinx Answer 21989).

- Why do I see the Run-Time configurable option for an 8-point FFT only when I recustomize the core? See (Xilinx Answer 29420).

- Why is the first data frame after a multi-cycle reset is incorrect? See (Xilinx Answer 24436).

- Why are the output results of the Pipelined Streaming I/O xFFT architecture not symmetrical? Or why do I see differences between the Radix-2 Minimum Resource implementation and the Pipelined Streaming I/O FFT implementation? See (Xilinx Answer 23247).

- Why do the timing diagrams not show the 3 clock cycle delay of the indexing signals? See (Xilinx Answer 29449).

- Why do my FFT output results drift from the expected results and become increasingly more inaccurate the longer I simulate my design? See (Xilinx Answer 29561).

- Why does the Number Of Block RAM Per Stage parameter always reset to zero ("0") when I recustomize my core? See (Xilinx Answer 29562).

dinky123

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03-17-2008 12:49 AM

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"I think there is some problem in this virsion, i've checked all possible setings, bt it is giving diffrent results for same input."

go to this link

and see the text down the page about the FFT which is

- N/A

- CR 220574: For the Pipelined Streaming I/O architecture, overflow is signaled for frames with no overflow, preceding or following a frame with an overflow (overflow tainting next or previous frame)

- CR 220203: GUI displays incorrect resource estimates for DSP48 count

- CR 220655: For the Pipelined Streamlining I/O architecture, the core dumps incorrect output data after a reset event (SCLR asserted, or new NFFT value latched in). If two reset events occur less than ~40 CLK cycles apart, the second reset might be incomplete and the core might start generating output values (DV = 1) from an incomplete input frame

- Large FFT point size generation times. See (Xilinx Answer 21988).

- Placement Issues when targeting a Virtex-II, Virtex-II Pro, or Spartan-3 device. See (Xilinx Answer 20307).

- First frame after multi-cycle reset might be incorrectly marked as valid. See (Xilinx Answer 24436).

- Slice estimate and implementation results are different. See (Xilinx Answer 21989).

- Why do I see the Run-Time configurable option for an 8-point FFT only when I recustomize the core? See (Xilinx Answer 29420).

- Why is the first data frame after a multi-cycle reset is incorrect? See (Xilinx Answer 24436).

- Why are the output results of the Pipelined Streaming I/O xFFT architecture not symmetrical? Or why do I see differences between the Radix-2 Minimum Resource implementation and the Pipelined Streaming I/O FFT implementation? See (Xilinx Answer 23247).

- Why do the timing diagrams not show the 3 clock cycle delay of the indexing signals? See (Xilinx Answer 29449).

- Why do my FFT output results drift from the expected results and become increasingly more inaccurate the longer I simulate my design? See (Xilinx Answer 29561).

- Why does the Number Of Block RAM Per Stage parameter always reset to zero ("0") when I recustomize my core? See (Xilinx Answer 29562).

it mentions that there are bugs in the version that are resolved in v4 but my problem is I am using a virtex II device that doesn't support FFTv4.

I am using ise9.2i and modelsim XE III 6.2g. Other available versions for me are v2,2.1,3,3.1 or 1.1 for 64,256 and 1024 point transform as I need 1024 point transform in the end.

"Or we should contact xilinx for this virsion if there may be some specific resion."

Yes that's an option.

"have u checked my codes? i'm using radix-4 burst I/O as i have to save the resources for other modules also."

yes I have seen that. I am also using similar ones.

hope it gets solved soon.

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mdjawaidalam

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03-17-2008 01:11 AM

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03-11-2008

That means i will have to update my IP?

but when i update IP it says yr version is upto date, does it mean i will have to use ISE9.2i?

plz help

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I think both 9.1 and 9.2 have fixed the problems as the bugs were in older ISE versions but still there has to be still some problem with this FFT core as is evident from the results. If you find any alternate solution please let me know....Older versions of FFT do not have so much flexibility in choosing the parameters as this one...

dinky123

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03-17-2008 12:56 PM

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mdjawaidalam

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03-17-2008 03:47 PM

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03-11-2008

Have u got correct results for forward FFT?

what sould be the result(xk_re and xk_im) for 128 point fft, if i'm giving input xn_re="00000001" and xn_im="00000000"?

plz reply.

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dinky123

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03-18-2008 05:22 AM

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"Have u got correct results for forward FFT?

what sould be the result(xk_re and xk_im) for 128 point fft, if i'm giving input xn_re="00000001" and xn_im="00000000"?

plz reply."

No.. I just checked with giving two similar sequences consecutively. If you are giving all real values as 1 and all imaginary values as 0 then first of all your magnitude spectrum should be symmetrical about 0 in the frequency domain and phase spectrum antisymmetrical. You can just plot it in matlab and see. Also the trigonometric fourier transform( since your sine term is 0) of an impulse train is an impulse train with the impulses located at the fundamental frequency and it's harmonics. The amplitude at 0 frequency should be 1/2 the amplitudes in the harmonics.

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mdjawaidalam

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03-18-2008 08:45 AM

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03-11-2008

Thanks,

but if we see mathematically then it should be

xk_re=128(0000 0000 1000 0000) only for first index, and rest should be zero.

xk_im= 0(0000 0000 0000 0000) for all index.

I've checked it on matlab.

But what u r saying is also absolutely right. And i'm getting result as u r saying(still i've not checked) that real and imaginary part seems to be varring and all r nonzerow.

Then what exactly i'm missing, and how one can interprate these two diffrent results.

I think u have good knowledge of DSP so u can answer it.

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dinky123

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03-18-2008 09:41 AM

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you are absolutely right. it gives 128 as the first sample and rest as 0. Since you are feeding a train of impulses of finite length which is same as approximating a step function, it gives an approximation of impulse function in the frequency domain(not sinc, which it should give theoretically) means a signal of 0 frequency in the time domain will give a delta function at 0 frequency in the frequency domain. The width of the impulse is due to approximation of an infinite train of impulses into a finite one...

However, this is not the actual problem. I think we are drifting away from that. I really need a solution to my question . Thanks for your answers.

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end;

mdjawaidalam

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03-20-2008 06:27 AM

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03-11-2008

I'm just sending u my code for fft engine, plz have a look,

If there is something wrong with it then Plz Help. What exactly "Synplicity black box declaration" do? It should be in code or not?

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

Library XilinxCoreLib;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

Library XilinxCoreLib;

library UNISIM;

use UNISIM.VComponents.all;

entity row_fft is

port (

clk: IN std_logic;

ce: IN std_logic;

sclr: IN std_logic;

fwd_inv: IN std_logic;

fwd_inv_we: IN std_logic;

start: IN std_logic;

xn_re: IN std_logic_VECTOR(7 downto 0);

xn_im: IN std_logic_VECTOR(7 downto 0);

rfd: OUT std_logic;

xn_index: OUT std_logic_VECTOR(6 downto 0);

busy: OUT std_logic;

edone: OUT std_logic;

done: OUT std_logic;

dv: OUT std_logic;

xk_index: OUT std_logic_VECTOR(6 downto 0);

xk_re: OUT std_logic_VECTOR(15 downto 0);

xk_im: OUT std_logic_VECTOR(15 downto 0));

end row_fft;

use UNISIM.VComponents.all;

entity row_fft is

port (

clk: IN std_logic;

ce: IN std_logic;

sclr: IN std_logic;

fwd_inv: IN std_logic;

fwd_inv_we: IN std_logic;

start: IN std_logic;

xn_re: IN std_logic_VECTOR(7 downto 0);

xn_im: IN std_logic_VECTOR(7 downto 0);

rfd: OUT std_logic;

xn_index: OUT std_logic_VECTOR(6 downto 0);

busy: OUT std_logic;

edone: OUT std_logic;

done: OUT std_logic;

dv: OUT std_logic;

xk_index: OUT std_logic_VECTOR(6 downto 0);

xk_re: OUT std_logic_VECTOR(15 downto 0);

xk_im: OUT std_logic_VECTOR(15 downto 0));

end row_fft;

architecture Behavioral of row_fft is

component row_fft_core

port (

clk: IN std_logic;

ce: IN std_logic;

sclr: IN std_logic;

fwd_inv: IN std_logic;

fwd_inv_we: IN std_logic;

start: IN std_logic;

xn_re: IN std_logic_VECTOR(7 downto 0);

xn_im: IN std_logic_VECTOR(7 downto 0);

rfd: OUT std_logic;

xn_index: OUT std_logic_VECTOR(6 downto 0);

busy: OUT std_logic;

edone: OUT std_logic;

done: OUT std_logic;

dv: OUT std_logic;

xk_index: OUT std_logic_VECTOR(6 downto 0);

xk_re: OUT std_logic_VECTOR(15 downto 0);

xk_im: OUT std_logic_VECTOR(15 downto 0));

end component;

port (

clk: IN std_logic;

ce: IN std_logic;

sclr: IN std_logic;

fwd_inv: IN std_logic;

fwd_inv_we: IN std_logic;

start: IN std_logic;

xn_re: IN std_logic_VECTOR(7 downto 0);

xn_im: IN std_logic_VECTOR(7 downto 0);

rfd: OUT std_logic;

xn_index: OUT std_logic_VECTOR(6 downto 0);

busy: OUT std_logic;

edone: OUT std_logic;

done: OUT std_logic;

dv: OUT std_logic;

xk_index: OUT std_logic_VECTOR(6 downto 0);

xk_re: OUT std_logic_VECTOR(15 downto 0);

xk_im: OUT std_logic_VECTOR(15 downto 0));

end component;

--Synplicity black box declaration

attribute syn_black_box : boolean;

attribute syn_black_box of row_fft_core: component is true;

attribute syn_black_box : boolean;

attribute syn_black_box of row_fft_core: component is true;

begin

U121 : row_fft_core

port map (

clk => clk,

ce => ce,

sclr => sclr,

fwd_inv => fwd_inv,

fwd_inv_we => fwd_inv_we,

start => start,

xn_re => xn_re,

xn_im => xn_im,

rfd => rfd,

xn_index => xn_index,

busy => busy,

edone => edone,

done => done,

dv => dv,

xk_index => xk_index,

xk_re => xk_re,

xk_im => xk_im);

port map (

clk => clk,

ce => ce,

sclr => sclr,

fwd_inv => fwd_inv,

fwd_inv_we => fwd_inv_we,

start => start,

xn_re => xn_re,

xn_im => xn_im,

rfd => rfd,

xn_index => xn_index,

busy => busy,

edone => edone,

done => done,

dv => dv,

xk_index => xk_index,

xk_re => xk_re,

xk_im => xk_im);

end;

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##

the black box comment is there to tell the synthesis tool to not synthesize the code since there is already a netlist for the core.

The problems you're describing do not match any known issues. I would recommend that you move to the latest version of this IP however I wonder if there is something else going wrong with the control logic. It may help to create a WebCase with Xilinx tech support to get some more specific details and questions answered about the FFT core.

http://www.xilinx.com/support/clearexpress/websupport.htm

jeffreyh

Xilinx Employee

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03-21-2008 01:53 PM

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08-07-2007

The problems you're describing do not match any known issues. I would recommend that you move to the latest version of this IP however I wonder if there is something else going wrong with the control logic. It may help to create a WebCase with Xilinx tech support to get some more specific details and questions answered about the FFT core.

http://www.xilinx.com/support/clearexpress/websupport.htm

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Hello,

I am currently getting problem with 512-point Radix-2 burst IO FFT v 4.1 when targeting a Virtex4 device. The FFT core simulated fine as a standalone component but provided incorrect results when simulation the toplevel component (the input data to the FFT core were the same as the standalone simulation). I am using the ISE ver 9.1.0.3 and ModelSim 6.2g. Would you like to help me to figure out what is the problem? Any ideas and suggestions?

Thank you

Message Edited by risc5555 on 03-23-2008 11:08 AM

risc5555

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03-23-2008 11:06 AM - edited 03-23-2008 11:08 AM

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03-23-2008

I am currently getting problem with 512-point Radix-2 burst IO FFT v 4.1 when targeting a Virtex4 device. The FFT core simulated fine as a standalone component but provided incorrect results when simulation the toplevel component (the input data to the FFT core were the same as the standalone simulation). I am using the ISE ver 9.1.0.3 and ModelSim 6.2g. Would you like to help me to figure out what is the problem? Any ideas and suggestions?

Thank you

Message Edited by risc5555 on 03-23-2008 11:08 AM

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dinky123

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03-24-2008 06:39 AM

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03-16-2008

jeffreyh wrote:

the black box comment is there to tell the synthesis tool to not synthesize the code since there is already a netlist for the core.

The problems you're describing do not match any known issues. I would recommend that you move to the latest version of this IP however I wonder if there is something else going wrong with the control logic. It may help to create a WebCase with Xilinx tech support to get some more specific details and questions answered about the FFT core.

http://www.xilinx.com/support/clearexpress/websupport.htm

Thank you for this information. I tried almost all settings for the control logic but that doesn't make any difference. I want to ask another question. The FFT core gives the output in two's complement format so it means the first bit is a sign bit? There is no mention about sign bit in the datasheet.

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dinky123

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03-27-2008 10:43 AM

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03-16-2008

Hello,

Could anyone get any new result? I am still stuck on it. There is one statement in the fft v5 datasheet that the simulations run with 1 ps resolution. What does that mean and what I have to change then in the simulator? I am using modelsim XE 6.2g. My IP is updated. Please reply. I have heard that the core gives correct results on hardware test. Also I have not written any testbench. Do I have to write it myself or it is available from xilinx? There was no testbench file generated with the core generator output files.

Thanks in advance for any input...

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agustinmarquez

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04-08-2008 07:08 AM

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04-08-2008

hello, iam using 8 point fast fourier transform 4.1 core in my project and using ISE 9.2i and modelsimXE III/starter 6.1e.

i put in xn_re = 0000 0000 1000 0000 and xn_im = (all zeros) then the output is incorrect for different frame with the same input.

please help me!!! what is the problem?

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cheekin_marine

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06-30-2008 01:22 PM

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06-16-2008

type in vsim -t 1ps (work).(testbench)

(work) is the directory u specify when creating a new simulation, (testbench) is the top module i think

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balkris

Xilinx Employee

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08-11-2008 06:21 AM

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Hi try this project . I attached test bench file and complete project . you will get expected result according to FFT property

signal rstart: std_logic:='1';

signal runload: std_logic:= '1';

signal rfwd_inv: std_logic:='1';

signal rfwd_inv_we: std_logic:='1';

Regards

Balkrishan

Xilinix India

Thanks and Regards

Balkrishan

--------------------------------------------------------------------------------------------

Please mark the post as an answer "Accept as solution" in case it helped resolve your query.

Give kudos in case a post in case it guided to the solution.

Balkrishan

--------------------------------------------------------------------------------------------

Please mark the post as an answer "Accept as solution" in case it helped resolve your query.

Give kudos in case a post in case it guided to the solution.

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amila123

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10-07-2008 10:53 PM

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im amila. from enginerin fac of university of moratuwa.can u plz send me code 4 FFT. lts very urgent. l hav 2 submit a project 1 week from now.thannk u

amilanp@hotmail.com

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technovlsi

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11-25-2011 01:38 PM

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@balkrishaniitg wrote:

Hi try this project . I attached test bench file and complete project . you will get expected result according to FFT property

signal rstart: std_logic:='1';

signal runload: std_logic:= '1';

signal rfwd_inv: std_logic:='1';

signal rfwd_inv_we: std_logic:='1';

Regards

Balkrishan

Xilinix India

sir, i have tried to simutate ur test bench code "tb_row_fft, but in simulation it shows "0' result,as well as inputs are also "0". i have simulated it for 800us. moreover,u adviced to use "signal rstart: std_logic:='1';

signal runload: std_logic:= '1';

signal rfwd_inv: std_logic:='1';

signal rfwd_inv_we: std_logic:='1';" in vhdl code , but sir,if i already declared these,then in test bench,these inouts are omitted, & does not match with the proper testbench code . plz help me. i am struggling over it many days........

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I am also facing the same problem , had your problem solved. Can u tell me value of scale_sch in FFT and IFFT.

varun_agr

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01-03-2012 10:59 PM

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ywu

Xilinx Employee

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01-04-2012 05:53 AM

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11-28-2007

Piggybacking an almost 4 years old thread with 20 messages makes it very confusing and difficult for people to follow. Please start a new thread describe exactly what problem you are having and let's go from there.

@varun_agr wrote:

Cheers,

Jim

Jim