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Observer panospet
Observer
5,408 Views
Registered: ‎02-21-2012

Variable delay block in Sysgen

Hello,

 

is there any way to implement the simulink block "Variable Delay" in System Generator for DSP using xilinx blocks?

 

thank you,

panospet

 

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6 Replies
5,395 Views
Registered: ‎02-28-2011

Re: Variable delay block in Sysgen

You can use the addressable Shift register (initial vector 0 and max delay as you choose)

 

or you can use a Dual Port Ram with a depth of a power of 2 and have a negative offset at the address ports.

example:

Dual port Ram depth of 64:

data input at Port A

addra is driven by a counter (6 bits)

ena = 1

data Port B is always 0 (same data format as Port A)

enb = 0

addrb is driven by the same counter but the offset (your variable delay) is subtracted from the address using an addsub block (output must be set to 6 bits and truncation/wrapping)

the offset in this case is your variable delay - 1 (1 delay cus of the Dual Port RAM)

 

Regards Markus

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Observer panospet
Observer
5,390 Views
Registered: ‎02-21-2012

Re: Variable delay block in Sysgen

Hello again and thanks for your help.

 

I asked this question because I need to implement the vibrato effect, for a university project.

 

I designed these two implementations that you told me, they seem to work perfectly when I simulate in simulink. The problem is, that, when I download them in my fpga, they don't work...

 

I give a sound signal as input, and my output is exactly the same, as no effect takes place. This happens in both cases, the one with the RAM and the other using the addressable shift register. I repeat, the simulation in simulink works perfectly.

 

Any ideas of what is wrong?

I attach my two designs, as well as the needed matlab workspace which gives the "from workspace" input.

I work on a XUP Virtex II pro board.

 

Thank you

panospet

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5,384 Views
Registered: ‎02-28-2011

Re: Variable delay block in Sysgen

Hi panospet,

 

How do you download the design into the FPGA? Do you use an ISE project to compile?

I cannot find any PIN Locations or clocks in your design, so i asume you use ISE for that.

If you do not need any additional blocks except the simulink design you can directly generate the bitsream in simulink

for that add the clock pin location and frequency in the system generator block and add all pin location into the gateway blocks.

Some general things missing in ISE might be the PIN locations clock/ce connections. I can just guess though.

 

Regards Markus

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Observer panospet
Observer
5,373 Views
Registered: ‎02-21-2012

Re: Variable delay block in Sysgen

Hello again, and thank you for your reply.

 

I'm using this tutorial--->  http://www.mediafire.com/view/?byy3felx5jsl201


which I downloaded from here ---> http://www.xilinx.com/univ/xupv2p.html (the one before the last)

 

So, after generating the bitstream from sysgen, I download my design using a .bat batch file which invokes impact, and downloads the xupv2pro_wrapper.bit file into the FPGA. This bitstream is generated after the merge of my design's .ngc with the wrapper's .ngc. This wrapper provides the interface for the AC97 audio codec.

 

The fact is that in some other designs that I made, (without making any changes to the pins auto-generated) I had no problem and the effects worked perfectly. Why would it be a difference to this?

 

For any occasion, I attach the two .ucf files which are auto-generated from sysgen (sysgen uses also the plugin from the tutorial). The xupv2pro_wrapper.ucf is for the wrapper, generated by default in all cases, and the audio_cw.ucf is the auto-generated constraints file of my design.

 

If you understand anything better of how to use these ucf files to make it work it would be very helpful.

 

Thanks a lot,

panospet

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1,461 Views
Registered: ‎05-17-2018

Re: Variable delay block in Sysgen

Sir
I wanted to delay sinusoidal output by 0.005seconds
The clocking pulse is 25ns so i require a latancy of 200000 to do the same
But if i try to do this using default delay block (4 Nos. In series)and put this latancy of 50000 in each i am getting simulation output correct
But my code is not getting generated
What and how can i exactly model a delay block with 0.005seconds
Please tell me steps by step procedure
were i can use Addressable Shift register with counters
Or anything other method with LFSR and RAM block
Thanks you
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1,271 Views
Registered: ‎02-28-2011

Re: Variable delay block in Sysgen

Hi,

 

this depends on your requirements. Adding 200000 register is definately not the best option.

Your clock speed is 25ns, but most likely you dont need such a high time resolution. You can downsample the signal by a factor of X. Then you will "only" need 200000/X registers.

you can use a Fifo to get a fixed delay as well. Write your sine wave to the Fifo, then start reading aft your desired time.

The Fifo size needs to be chosen accordingly.

 

Regards Markus

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