cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
nixiebunny
Contributor
Contributor
634 Views
Registered: ‎01-26-2009

Vector FFT documentation regarding frames

I'm trying to understand how to use the Vector FFT that System Generator DSP creates.

I am using it in pipelined streaming mode, fixed length. I would like to stream data continuously through the FFT with no dropped words, but that's not absolutely necessary.

The Vector FFT block has tvalid and tready inputs and outputs. However, there is no reset signal, no start signal, no tlast signal, no output index, nothing at all to provide a clue to the frame start point. (The Fast Fourier transform IP Core 9.1 has these features, so it's a bit easier to use.)

How is a user supposed to synchronize the FFT frames of a Vector FFT?

 

4 Replies
arashr
Explorer
Explorer
560 Views
Registered: ‎02-06-2018

Hi

I have the same question, in a regular FFT, it provides start_frame_in and start_frame_out pins:

FFT.pngBut for the SSR FFT there is no control pins:

VFFT.png

So my question is, how to make sure the SST FFT is synchronized and how to control/monitor the frame's start and stop states?

 

 

0 Kudos
vkanchan
Xilinx Employee
Xilinx Employee
207 Views
Registered: ‎09-18-2018

Hi ,

The start of an input frame is indicated by a rising transition on input_valid port. Once this signal goes high, the input_valid signal cannot drop low until entire frame data of 'N' (fft size) samples is input to the core. 
The input valid can go low between each frame, but once frame is started, it should be high until input frame is completely sent into the core else the output will be corrupted. 

This information is missing in the SSR FFT documentation. It will be updated in future release.

0 Kudos
arashr
Explorer
Explorer
139 Views
Registered: ‎02-06-2018

@vkanchan Thank you. So, to understand it better, if input_valid goes down before the entire frame is transferred, the output will be corrupted (as you said), but is there any way to restart the IP core to restart transmitting the frame?

0 Kudos
vkanchan
Xilinx Employee
Xilinx Employee
114 Views
Registered: ‎09-18-2018

Hi @arashr ,

No there is no other way  to restart the transmission. The input frame has to be resent to the core again to get the entire correct output frame again.