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Explorer
Explorer
757 Views
Registered: ‎03-31-2016

Virtex6 Implementation error(PhysDesignRules:2468)

Hello

 

Used xc6vlx760-1ff1760 to implementation my design, but ISE report PhysDesignRules:2468 error message.

 

How to resolve this issue?

 

ISE version is 14.4

 

 

 

PhysDesignRules:2468 - DSP48E1 block ../U_PAPR_X_COEFA_PRE_MULT/genblk2.U_MULT_26X19/blk00000001/blk00000004 has incomplete PCOUT connectivity. The PCOUT pin connectivity must drive to the corresponding PCIN pin of the DSP48E1 block directly above it and a DSP48E1 block with PCIN pin connectivity was not found. The PCOUT pins must be properly connected or the signal for the PCOUT pin(s) must be removed.

 

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3 Replies
714 Views
Registered: ‎06-21-2017

Re: Virtex6 Implementation error(PhysDesignRules:2468)

Is that DSP slice instantiated, inferred or part of a core?  In any case, PCOUT can only drive PCIN of the next slice in the column.  If it is connected to anything else, or if it is the last DSP slice in the column, the routing will fail with this message.

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Explorer
Explorer
682 Views
Registered: ‎03-31-2016

Re: Virtex6 Implementation error(PhysDesignRules:2468)

Hello @bruce_karaffa

 

In the below, it's DSP schematic, i don't used blk00000004 PCOUT port, but ISE report error message.

 

How to resolve this issue?

 

Note: This DSP is used ISE 14.4 coregen to generator.

 

 

Virtex6_DSP.JPG

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674 Views
Registered: ‎06-21-2017

Re: Virtex6 Implementation error(PhysDesignRules:2468)

I would have thought that the PCOUT of the second DSP would have been trimmed since it isn't being used.  There are a couple work arounds.  The schematic is telling you exactly what is going into every input of each DSP. You could just code this in your favorite RTL and leave the second PCOUT OPEN.  You could just use the multiply operator in your code and let the synthesizer worry about how to connect this.  

 

Maybe somebody from Xilinx has a thought ojn why there is a stub hanging off of the second DSP.

 

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