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675 Views
Registered: ‎03-07-2019

Viterbi Decoder

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Hi,

I would like to decode 500 (encoded by a convolution encoder with 1 / 2 rate and a constraint length of 7) bits by using Viterbi decoder (IP core) to get 250 bits output. 

Configuration of the Viterbi Decoder IP core in the Block Design:

Standard Viterbi Type, Constraint Length 7, Traceback length 96, Parallel Architecture, Best State is not used, No Puncturing, Hard Coding, convolution codes are (1011011 and 1111001), BER symbol count is not used.

- However I do not know how many bits I will give the viterbi decoder to get outputs I desired.

In my opinion, viterbi decoder  operates on continuous bit stream. I have to know the starting and finishing points of the trellis.Because I dont want to operate it as continuous bit stream. Am I correct?

Each time I call my function, viterbi decoder will decode 500 bits to get 250 bits. I put the input as  500 + traceback lenght , it did not work. I put the input as  traceback lenght + 500 + traceback lenght , It did not work. 

Thanks in advance

 

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Moderator
Moderator
515 Views
Registered: ‎08-01-2007

回复: Viterbi Decoder

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The order of outputs matches the order of inputs.

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11 Replies
Moderator
Moderator
649 Views
Registered: ‎08-01-2007

回复: Viterbi Decoder

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You are correct that Viterbi decoder operates continuous bit stream, but Viterbi decoder can also be used to operate on block decoding, XAPP551 provides several ways to implement block decoding. Basically it helps to dertermine the trellis start and end state. Have you read XAPP551? 

 

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Registered: ‎03-07-2019

回复: Viterbi Decoder

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I have read XAPP551. There are tail biting and trellis truncation methods to dertermine the trellis start and end state. That is what I searching for. I have 500 bits to decode. But if my understanding correct I have to give multiple of traceback lenght bits to decoder to decode it correctly , If I use tail biting. If  I use trellis truncation method It makes the doceder start with zero state to decode it correctly. Still I am not sure which method I will use. 

Because I expect that the decoder will operate as  :

                        İnput: tb_lenght + 500 + tb_lenght  -> Viterbi Ip core -> Output: tb_lenght/2 + 250 + tb_lenght/2    

when I use it as standart mode , parallel architecture. But it gives nothing. It gives some bits after latency time. This case it is 198 inputs. It gives something after 198 input comes to decoder. I do not know how I will manage this.

Do you have any idea?

 

Thank in advance.  

tail biting.PNG
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Moderator
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Registered: ‎08-01-2007

回复: Viterbi Decoder

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It's just because you don't send enough data into the decoder, the Figure you put here is for data packet equals to multiple traceback length, you can try to get your packet to be multipler traceback length. The other thing is to check if the decoder parameter settings are the same with encoder. You can build a simple test case for trellis termiation or tail biting with encoder and decoder together to verify this one.

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Registered: ‎03-07-2019

回复: Viterbi Decoder

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It's just because you don't send enough data into the decoder, (But I do not want to send that much input into the decoder, Should I zero-pad rest of the sequence, or Should I send my input two or tree or four ( until I get outputs . . .) times into the decoder. Because I have small number of inputs. How will I handle this issue? Do you have any idea?  ) the Figure you put here is for data packet equals to multiple traceback length, you can try to get your packet to be multipler traceback length (I can choose traceback lenght as devider of my input lenght, Yes you are right). The other thing is to check if the decoder parameter settings are the same with encoder. You can build a simple test case for trellis termiation or tail biting with encoder and decoder together to verify this one (My viterbi decoder parameters are the same with convolutional encoder's).

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589 Views
Registered: ‎08-01-2007

回复: Viterbi Decoder

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You can try to get your packet to be multipler traceback length.

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Registered: ‎03-07-2019

回复: Viterbi Decoder

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Viterbi requires minimum number of inputs. This minimum number is two times traceback lenght, right? It is written in PG027 document. But when I send two times traceback lenght inputs into the decoder, It gives nothing. There is latency for the output. And this latency is much more than my input. As I understand , I have to send inputs more than latency and my input packed should be multipler of traceback lenght. Is my opinions correct? 

 

Thank you.

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Moderator
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554 Views
Registered: ‎08-01-2007

回复: Viterbi Decoder

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This may due to best state not being selected.

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Registered: ‎03-07-2019

回复: Viterbi Decoder

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Ok  I will try it. Assume that I have inputs like these (Figure). After some latency, I will have outputs. I wonder that what the direction of trellis construction and direction of traceback is. I mean , are my first outputs  decoded first inputs? How does the decoder work in case of direction of trellis construciton and traceback? 

 

Thank you for your supports. 

Capture.PNG
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Moderator
Moderator
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Registered: ‎08-01-2007

回复: Viterbi Decoder

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The order of outputs matches the order of inputs.

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511 Views
Registered: ‎03-07-2019

回复: Viterbi Decoder

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Okey. I solved my problems. Viterbi decoder works now. Thank you for everything.

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Newbie raohong
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219 Views
Registered: ‎07-26-2019

回复: Viterbi Decoder

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Could you please share the solution for me because I met the same problem .Thank you very much.

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