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iguaner
Observer
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6,707 Views
Registered: ‎07-20-2009

Vivado 2013.3 Multirate implementation

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Hello

 

I have a System Generator design created in Vivado 2013.3. The design uses two sample rates - in HW 400 and 200 MHz. I want use Multirate implementation "Expose Clock Ports" (as with ISE) but the checkbox is allways gray (not accesible). What can cause this problem and is there any solution how to use "Expose Clock Ports"?

 

Thanks for any help

Ondrej

 

 

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vsrunga
Xilinx Employee
Xilinx Employee
9,554 Views
Registered: ‎07-11-2011

Hi,

 

I referred UG897, please refer page page 48 onwards so that you may find info on multiple clock handling, if it applies for you.

 

Regarding UG958 , it could be a documentation fault which will be correced in next release if the feature is not added.

 

 

Regards,

Vanitha.

 

 

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iguaner
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Registered: ‎07-20-2009

Hi

 

tnaks for your reply.

 

My Matlab version is 2013b 64bit and my OS is Windows 7 64 bit. I have tested new project with Zynq 020 and the "demo" project created after selecting "Add source" > "Add or create DSP source" > "Create subdesign" (see snapshot). I have the same problem on two different machines (same OS, Vivado and Matlab version).

 

Sorry for using 7z but I am not able to upload zip file.

 

Ondrej

vivado_sysgen_err.png
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vsrunga
Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

Your observation seems correct.

I  do not see "Expose clock ports" description in Vivado Sysgen user guide so expect this option was removed .

Few ISE features were under development in Vivado.

Will report it as an Enhancement requirement, as a workaround I think you can manually include the clock ports in the HDL netlist wrapper for the clock signals or use ISE Sygen if your design permits.

 

 

 

Regards,

Vanitha.

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iguaner
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Registered: ‎07-20-2009

Hi

 

What user guide are you referring to? I have looked in UG958 (v2013.3) October 2, 2013 page 288 and there is written:

 

Multirate implementation:

° Clock Enables (default): Creates a clock enable generator circuit to drive the

multirate design.

° Expose Clock Ports: This option exposes multiple clock ports on the top-level of

the System Generator design so you can apply multiple synchronous clock inputs

from outside the design.

 

Ondrej

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vsrunga
Xilinx Employee
Xilinx Employee
9,555 Views
Registered: ‎07-11-2011

Hi,

 

I referred UG897, please refer page page 48 onwards so that you may find info on multiple clock handling, if it applies for you.

 

Regarding UG958 , it could be a documentation fault which will be correced in next release if the feature is not added.

 

 

Regards,

Vanitha.

 

 

---------------------------------------------------------------------------------------------
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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

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iguaner
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Registered: ‎07-20-2009

Hi

 

thanks for your reply. You are right - the UG897 says (page 36): "As shown in the figure below, when you use the System Generator token to compile a design into hardware, there is one clocking option for Multirate implementation: (1) Clock Enables (the default)."

 

Now I know I cant expect "Expose clock" option in Vivado and I have to switch back to ISE System Generator.

 

Ondrej

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