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Observer trungnguyen
Observer
179 Views
Registered: ‎05-04-2018

Vivado 2018.3 Simulation error with LDPC core

Dear all,

I am running simulation with LDPC core. My system requires 2 LDPC cores running in parallel, somehow like following pictures.

din_1 => LDPC_1 => ..

                                             => COMBINE => dout

din_2 => LDPC_2 => ..

 

I would like to write a testbench which:

- Read data from a file

- Then pass it to din_1 and din_2 in specific order

The following is my code:

p_stimulus: process 
        variable v_line: line;
        variable v_data: STD_LOGIC_VECTOR(127 downto 0);
        variable v_counter : natural := NUM_COUNTER;
        variable sel_channel_1: STD_LOGIC;
        variable sel_channel_2: STD_LOGIC;
    begin 
        sel_channel_1 := '1';
        sel_channel_2 := '0';
wait until clk'event and clk = '1' and rst_n = '1' and s_axis_din_channel_1_tready = '1';
loop if endfile( f_din ) then s_axis_din_channel_2_tvalid <= '0'; s_axis_din_channel_1_tvalid <= '0'; assert false report "End of file encountered; exiting ..." severity NOTE; wait; exit; end if; readline(f_din, v_line); read(v_line, v_data); if (sel_channel_1 = '1') then s_axis_din_channel_1_tdata <= v_data; s_axis_din_channel_1_tvalid <= '1'; s_axis_din_channel_2_tvalid <= '0'; elsif (sel_channel_2 = '1') then s_axis_din_channel_2_tdata <= v_data; s_axis_din_channel_2_tvalid <= '1'; s_axis_din_channel_1_tvalid <= '0'; end if; if (v_counter = 1) then if (sel_channel_1 = '1') then s_axis_din_channel_1_tlast <= '1'; elsif (sel_channel_2 = '1') then s_axis_din_channel_2_tlast <= '1'; end if; else if (sel_channel_1 = '1') then s_axis_din_channel_1_tlast <= '0'; elsif (sel_channel_2 = '1') then s_axis_din_channel_2_tlast <= '0'; end if; end if; v_counter := v_counter - 1; if (sel_channel_1 = '1') then wait until (clk'event and clk = '1' and s_axis_din_channel_1_tready = '1'); s_axis_din_channel_1_tvalid <= '0'; elsif (sel_channel_2 = '1') then wait until (clk'event and clk = '1' and s_axis_din_channel_2_tready = '1'); s_axis_din_channel_2_tvalid <= '0'; end if; if (sel_channel_1 = '1') then s_axis_din_channel_1_tlast <= '0'; elsif (sel_channel_2 = '1') then s_axis_din_channel_2_tlast <= '0'; end if; if (v_counter = 0) then v_counter := NUM_COUNTER; sel_channel_1 := not sel_channel_1; sel_channel_2 := not sel_channel_1; end if; end loop; end process p_stimulus;

Doing so, I got weird behavior of LDPC core which is tready of LDPC data port becomes X whole time.

111111.png

 

In another testbench version, when I deleted the line of code as in the following

p_stimulus: process 
        variable v_line: line;
        variable v_data: STD_LOGIC_VECTOR(127 downto 0);
        variable v_counter : natural := NUM_COUNTER;
        variable sel_channel_1: STD_LOGIC;
        variable sel_channel_2: STD_LOGIC;
    begin 
        sel_channel_1 := '1';
        sel_channel_2 := '0';

     --   wait until clk'event and clk = '1' and rst_n = '1' and s_axis_din_channel_1_tready = '1';

        loop
....

Then, the core running as expectation - No X at ldpc_tready.

 

Could someone help me to clarify this issue? What is the cause - (to help me avoid the same issue in the future)

 

Thanks,

Trung Nguyen

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1 Reply
Moderator
Moderator
58 Views
Registered: ‎08-01-2007

回复: Vivado 2018.3 Simulation error with LDPC core

This is due to that S_axis_din_tvalid input. is not forced to ZERO. I'd recommend to assert reset during the first 20 clock cycles, when the reset is asserted, make sure all the inputs are initilization to zero in the simulation.

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