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03-21-2011 04:23 AM
I designed the digital controller usin XSG blocks.It works fine.The problem is that it offerd total path delay of 33 ns.
I have Spartan 3E Board.it offers clock frequency of 50 MHz,equivalent to 20 ns.The path delay should be less than this clock period (20 ns).First I want to generate hw cosim block and then want to use it for the hardware/software cosimulation. I can't simplyfy further my algorithm to reduce the path delay. How can I solve this problem?Please help me,I am confused.
All I want to use hardware in loop and I had Spartan 3E.