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Visitor xc2vp30
Visitor
14,565 Views
Registered: ‎11-05-2007

constraints problem ???

I use the Audio Design with v8.2 System Generator for DSP (you can download it on the xilinx page (http://www.xilinx.com/univ/xupv2p.html)) as a base for my project. I needed the ac97 codec and it worked. After I had checked the function of the codec I wanted to use a button and a led in the model.
1.Step
Define and initialization of the constraints over Gatway, with the "Specify IOB location constraints" - field
I can compile the model and I get the bitstream. I checked also the ucf-file, what get generate from the SystemGenerator, during generation and I could see the right entries.
I draged the bitstream on the FPGA but the butten dosen't work.
2.Step
Define and initialization of the constraints over BSP (Board Support Package) (yourboard.ucf) in this case the file is called xupv2pro_wrapper.ucf and it look like:

Net clk_in LOC="AJ15";
Net clk_in IOSTANDARD = LVCMOS25;
Net clk_in PERIOD = 10000 ps;

Net reset_in LOC="AG5";
Net reset_in IOSTANDARD = LVTTL;
Net reset_in TIG;

NET AC97Clk PERIOD = 81.38 ns;
NET "AC97Clk" TNM_NET = "ac97bitclk_grp";

### AC97 Signals ###
NET AC97Clk       LOC = "F8";
NET AC97Reset_n   LOC = "E6";
NET Sync          LOC = "F7";
NET SData_Out     LOC = "E8";
NET SData_In      LOC = "E9";

NET AC97Clk       IOSTANDARD = LVTTL;
NET AC97Reset_n   IOSTANDARD = LVTTL;
NET Sync          IOSTANDARD = LVTTL;
NET SData_Out     IOSTANDARD = LVTTL;
NET SData_In      IOSTANDARD = LVTTL;

NET AC97Reset_n   DRIVE = 8 | SLEW = SLOW;
NET Sync          DRIVE = 8 | SLEW = SLOW;
NET SData_Out     DRIVE = 8 | SLEW = SLOW;


# Global period constraint
#NET "clk" TNM_NET = "clk_7f1f9c47";
#TIMESPEC "TS_clk_7f1f9c47" = PERIOD "clk_7f1f9c47" 40.0 ns HIGH 50 %;

# ce_4_7f1f9c47_group and inner group constraint
#Net "*ce_4_sg*" TNM_NET = "ce_4_152dfcd7_group";
#TIMESPEC "TS_ce_4_152dfcd7_group_to_ce_4_152dfcd7_group" = FROM "ce_4_152dfcd7_group" TO "ce_4_152dfcd7_group" 20833.33 ns;

###############################################################
######TEST/TEST/TEST/TEST/TEST/TEST/TEST/TEST##################
###############################################################

#LED

NET l3net LOC = "AA5";               #That are the LED's and the button's I would like to use
NET l2net LOC = "AA6";               #My first thought was that the name behind the NET is
NET l1net LOC = "AC3";              #the name I have to give the gareway in the model and than it would work
NET l0net LOC = "AC4";              #???

#Button

NET anet LOC = "AH4";
NET bnet LOC = "AH2";
NET cnet LOC = "AH1";

When I try to generate the model I get an error, how looks like:

Applying constraints in "xupv2pro_wrapper.ucf" to the design...

ERROR:NgdBuild:755 - "xupv2pro_wrapper.ucf" Line 44: Could not find net(s)

   'l3net' in the design.  To suppress this error specify the correct net name

   or remove the constraint.  The 'Allow Unmatched LOC Constraints' ISE property

   can also be set ( -aul switch for command line users).

ERROR:NgdBuild:755 - "xupv2pro_wrapper.ucf" Line 45: Could not find net(s)

   'l2net' in the design.  To suppress this error specify the correct net name

   or remove the constraint.  The 'Allow Unmatched LOC Constraints' ISE property

   can also be set ( -aul switch for command line users).

ERROR:NgdBuild:755 - "xupv2pro_wrapper.ucf" Line 46: Could not find net(s)

   'l1net' in the design.  To suppress this error specify the correct net name

   or remove the constraint.  The 'Allow Unmatched LOC Constraints' ISE property

   can also be set ( -aul switch for command line users).

ERROR:NgdBuild:755 - "xupv2pro_wrapper.ucf" Line 47: Could not find net(s)

   'l0net' in the design.  To suppress this error specify the correct net name

   or remove the constraint.  The 'Allow Unmatched LOC Constraints' ISE property

   can also be set ( -aul switch for command line users).

ERROR:NgdBuild:755 - "xupv2pro_wrapper.ucf" Line 51: Could not find net(s)

   'anet' in the design.  To suppress this error specify the correct net name or

   remove the constraint.  The 'Allow Unmatched LOC Constraints' ISE property

   can also be set ( -aul switch for command line users).

ERROR:NgdBuild:755 - "xupv2pro_wrapper.ucf" Line 52: Could not find net(s)

   'bnet' in the design.  To suppress this error specify the correct net name or

   remove the constraint.  The 'Allow Unmatched LOC Constraints' ISE property

   can also be set ( -aul switch for command line users).

ERROR:NgdBuild:755 - "xupv2pro_wrapper.ucf" Line 53: Could not find net(s)

   'cnet' in the design.  To suppress this error specify the correct net name or

   remove the constraint.  The 'Allow Unmatched LOC Constraints' ISE property

   can also be set ( -aul switch for command line users).

ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.

ERROR:NgdBuild:19 - Errors found while parsing constraint file

   "xupv2pro_wrapper.ucf".



Writing NGDBUILD log file "xupv2pro_wrapper.bld"...

ERROR:Xflow - Program ngdbuild returned error code -1. Aborting flow

   execution...



Do you know why the button dosen't work in the first case? I think it has something to do with the translation of the wrapper-file .ngc and the netlist-file from the sysgen .ngc.
Do you know how I can get the conection between the gateway (button or LED) and the Pin-locatin-constraints?
I tryed to trace the way of the used gateways but i didn't found the link between them.

Thanks for your time
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6 Replies
Highlighted
Visitor jacobusn
Visitor
14,560 Views
Registered: ‎08-15-2007

Re: constraints problem ???

Hi

If you just want to generate the design to a bitstream and run it stand-alone it should work when you specify the pin locations in the IOB's themselves. Do you get the messages when you generate your design in SysGen? or when you run the HDL from your sysgen design through the flow in ISE/command line? You should be able to get those net names when you have a look at the RTL schematic of your sysgen HDL's top level.

I'm not sure why you mention the SysGen board support package when you don't use Hardware Co-Simulation. Maybe I misunderstood you. If you want to use hardware cosimulation, I think you are using the board support package incorrectly. You should not need to define those net names manually. In the xup_virtex_ii_pro.zip board plugin there is a file called zup_virtex_ii_pro_libgen.m which will create a library containing all your non-memory mapped ports for the board. When you place these in your design and compile it those ports should be LOC'ed to the correct pins automatically.

Cheers
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Visitor xc2vp30
Visitor
14,540 Views
Registered: ‎11-05-2007

Re: constraints problem ???

hi   jacobusn

when you say "specify the pin locations in the IOB's themselves", do you mean inside the sysgen model in the Xillinx gateway? The tab is called Implementation and you can hook the box called "Specify IOB location constraints" and then you can give them the right pin location like {'AH4'} (button), that  is the way it works usually. If you mean that, than I can say yes that was my first try. After generat the model, I  looked up the constraints in the log-file (xupv2pro_XXX_pad) and I saw that the pin-location got changed to a another pin-location for example from AH4 to EH9.That happens only  when I use the  Audio Design with v8.2 System Generator for DSP modle.
I don't get any messages in this case. The sysgen or ise works without errors.
I looked up the RTL schematic and the button and the LED are conected. But the constraints not needed until the programm starts to map.

The zup_virtex_ii_pro_libgen.m is as you said a JTAG CO-Simulation BSP. But I think when you want to generate the bitstream you need the full deployment  BSP. For example: I needed the ac97 codec but with a nother configuration. I had to generate a new xupv2pro_wrapper.ngc and that is in my opinion one of the full deployment  BSP. This is all explaint in a power point presentation called "system generator for dsp board support package / xup virtex-II pro". I think you can find it in the zip file.

xc2vp30
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Visitor xc2vp30
Visitor
14,518 Views
Registered: ‎11-05-2007

Re: constraints problem ???

Hi @ all.

Does somebody know somethink about this bug?

#----------------------------------------------#

# Starting program bitgen

# bitgen -l -w -m -intstyle xflow xupv2pro_wrapper.ncd

#----------------------------------------------#

WARNING:PhysDesignRules:367 - The signal <a_IBUF> is incomplete. The signal does

   not drive any load pins in the design.

ERROR:PhysDesignRules:368 - The signal <l3_OBUF> is incomplete. The signal is

   not driven by any source pin in the design.

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance

   with the CLKFX and CLKFX180 outputs of the DCM comp

   Inst_ClockGen/Inst_ClockGen/DCM_INST/Inst_ClockGen/DCM_INST, consult the

   device Interactive Data Sheet.

ERROR:PhysDesignRules:10 - The network <l3_OBUF> is completely unrouted.

ERROR:Bitgen:25 - DRC detected 2 errors and 1 warnings.

ERROR:Xflow - Program bitgen returned error code 1. Aborting flow execution...

a should be a button (input) and l3 should be a led (output)
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Observer manganganath
Observer
8,327 Views
Registered: ‎07-13-2009

Re: constraints problem ???

Can someone please tell me where to download "xup_virtex_ii_pro.zip"? Thanks in advance.
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Observer veiledcavalier
Observer
8,218 Views
Registered: ‎09-13-2007

Re: constraints problem ???

5,357 Views
Registered: ‎02-09-2011

Re: constraints problem ???

Hi,

I designed the digital controller usin XSG blocks.It works fine.The problem is that it offerd total path delay of 33 ns.

I have Spartan 3E Board.it offers clock frequency of 50 MHz,equivalent to 20 ns.The path delay should be less than this clock period (20 ns).First I want to generate hw cosim block and then want to use it for the hardware/software cosimulation. I can't simplyfy further my algorithm to reduce the path delay. How can I solve this problem?Please help me,I am confused.

All I want to use hardware in loop and I had Spartan 3E.

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