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Explorer
Explorer
3,744 Views
Registered: ‎07-25-2016

simulink system period

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Hi all,

 

I have a design in System generator and going to implement it on the ZED board. I have run the timing analysis and the result says that there is no timing violation. I see an option 'Simulink system period(sec) ' set to 1(default) in clocking option of system generator icon(shown in figure below). My question is, what value should it be changed to ? what determines the simulink system period?

 

thank you in advance.

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Xilinx Employee
Xilinx Employee
6,419 Views
Registered: ‎05-07-2015

Re: simulink system period

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HI @sai_shashi

 

Hope your query is addressed. As long as you are not designing the multi sample rate system. you can keep all the sample period values as '1' (in sysgen token and in Gateway in blocks)and work .

Thanks
Bharath
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Xilinx Employee
Xilinx Employee
3,731 Views
Registered: ‎08-02-2011

Re: simulink system period

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The timing analysis will be performed against the requirement set in the 'FPGA clock period.' The simulink system period is basically a normalization factor to make sample rate math easier in the simulink environment. It won't affect the timing analysis.

www.xilinx.com
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Explorer
Explorer
3,717 Views
Registered: ‎07-25-2016

Re: simulink system period

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thanks for your reply.

 

But will the simulink system period affect the hardware co-simulation timing. I mean by reducing the simulink system period will we be able to accelerate the design ? or what are the other parameters that the acceleration through hardware co-simulation depends upon ? 

 

than you

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Xilinx Employee
Xilinx Employee
3,601 Views
Registered: ‎08-01-2008

Re: simulink system period

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check jtag frequency settings
Thanks and Regards
Balkrishan
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Explorer
Explorer
3,597 Views
Registered: ‎07-25-2016

Re: simulink system period

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where do i check jtag frequency settings ?

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Xilinx Employee
Xilinx Employee
3,595 Views
Registered: ‎08-01-2008

Re: simulink system period

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in generated hardware co simulation settings .
Thanks and Regards
Balkrishan
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Explorer
Explorer
3,594 Views
Registered: ‎07-25-2016

Re: simulink system period

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Hi

I have connected the zed board to PC through JTAG port.

In HWcosim settings editor window, the fields are inactive. whats is the reason? 

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Xilinx Employee
Xilinx Employee
3,586 Views
Registered: ‎05-07-2015

Re: simulink system period

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HI @sai_shashi

Simulink system period  will not affect either HW cosimulation or the normal simulation speed. As Brian wiec, it is just a normalized value of the sample period value. and can be left at 1 if your entire simulink design works at one sample rate.

Only when your design involves multiple sample rates , the simulink sample period should be  the greatest common divisor of all the sample periods in the model.

Thanks
Bharath
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Xilinx Employee
Xilinx Employee
6,420 Views
Registered: ‎05-07-2015

Re: simulink system period

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HI @sai_shashi

 

Hope your query is addressed. As long as you are not designing the multi sample rate system. you can keep all the sample period values as '1' (in sysgen token and in Gateway in blocks)and work .

Thanks
Bharath
--------------------------------------------------​--------------------------------------------
Please mark the Answer as "Accept as solution" if information provided addresses your query/concern.
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View solution in original post

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