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Observer
Observer
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Registered: ‎11-21-2018

system generator

Hi, 

I create some block on the system generator with some AXI4-lite read/write registers. in the original the system clock and AXI-Bus clock is 40MHz. 

I want to increase only the AXI bus clock to 100MHz. 

This registers can be updtae by the ZYNQ and by the subsystem in the IP, my questions how to syncronize these registers in the system generator?

How to connect the new clock in the VIVADO block diagram?

Thank you.

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Moderator
Moderator
363 Views
Registered: ‎08-16-2018

Re: system generator

Below is what I understood, 

You have certain SysGen design where the frequecy is set to 40 MHz (or some other) in sysgen token. Next, you generated the IP for this design and using it with znyq.  Now, you want to use the IP at 100 MHz. 

---

If above is the correct question, then all you need to do is "change the frequency in the constraint files in Vivado project". No changes are required in the SysGen design. 

 


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
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Observer
Observer
341 Views
Registered: ‎11-21-2018

Re: system generator

Hi,

No it's not what i need, I have in the IP, AXI-lite register ( which created by using In-Gate and Out-gate) , I want to change ONLY the clock on the AXI-lite registers.

If i change the system clock, It will require to change almost each block which I have on the IP , (because I'm using constant with Relational).

I need multiple clock domain, one for the IP logic and faster clock for the AXI-Lite registers. 

I tired to do the example on the Lab 4:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug948-vivado-sysgen-tutorial.pdf

It's not a good solution for my design.

Thank you,

Avi 

 

 

 

 

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Moderator
Moderator
285 Views
Registered: ‎08-16-2018

Re: system generator

In Vivado, you can change the clock-period in the .xdc file which is generated by the System Generator.

/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
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