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Scholar
Scholar
968 Views
Registered: ‎04-04-2014

why is my xfft output not full scale?

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Hi,

 

I am using an XFFT core in forward FFT mode, unscaled. According to the PG the expected output width is equal to input_width+ log2(transform length) +1. I have 16 bits input and a 256 length fft, so I expect 25 bits out.

 

However, in all my sims I have never seen that 25th bit used. My highest output is achieved when I put a full power DC signal in and this still only uses 24 bits. Have I made a mistake? If not, what conditions would exercise this bit? 

 

As it stands my dB calculation has my highest possible power recorded at -6dB because of this...

 

Thanks

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Moderator
Moderator
877 Views
Registered: ‎08-01-2007

Does the reply answer your question? If it answers, please give kudos or accept as solutions.

 

The maximum constant input is not the worst case input scenario for bit growth. You can have a look at "Finite Word Length Considerations" section on PG109.

 

 

 

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Xilinx Employee
Xilinx Employee
945 Views
Registered: ‎08-02-2007

have you tried with a different architecture?

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Scholar
Scholar
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Registered: ‎04-04-2014

@liy wrote:

have you tried with a different architecture?


What do you mean? What aspect of the configuration do you suggest changing? 

 

To be honest, I don't really want to have to try an assortment of different configurations to determine which one does what the PG says. Building thew IP and simulating takes a decent amount of time, this sounds like a surefire way to chew up an entire day. The PG is pretty clear that full bit growth leads to 25 bits of output. Do you know why this might not be the case? 

 

Thanks

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Xilinx Employee
Xilinx Employee
904 Views
Registered: ‎08-02-2007

you may need to use Matlab to verify if this is the Max

the output  also related to the coefficient so the full DC may not be the worst case

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Scholar
Scholar
885 Views
Registered: ‎04-04-2014

@liy wrote:

you may need to use Matlab to verify if this is the Max

the output  also related to the coefficient so the full DC may not be the worst case


Ok thanks. To be honest, we apply gain correction to account for real signal losses on the PCB so the 6dB offset won't be an issue in the long run, I was just interested into why this happened.

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Moderator
Moderator
878 Views
Registered: ‎08-01-2007

Does the reply answer your question? If it answers, please give kudos or accept as solutions.

 

The maximum constant input is not the worst case input scenario for bit growth. You can have a look at "Finite Word Length Considerations" section on PG109.

 

 

 

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View solution in original post