I have implemented a network on Xilinx MPSoC board and I ran "vaitracer" tool to get the required files for analyzing the design. I have a question now:
As you see, in the DDR read/write rate, I have multiple graphs in the same plot. However, I don't know what are those DDRC ports. Can you please clarify what are those ports and why the model uses some ports more than others? As I researched this is DDR Controller but I didn't get more details about them. I think there is a big picture that I am missing!