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Contributor
Contributor
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Registered: ‎09-19-2018

DPU TRD for ZCU104 ?

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Hi, I would like to use DPU TRD in ZCU104 but at the download page (https://www.xilinx.com/products/design-tools/ai-inference/ai-developer-hub.html#edge) I can only see this file: zcu102-dpu-trd-2018-2-190322.zip, which seems to be the IP for ZCU102 board.

So my question is: is this IP available for ZCU104 board ?

Regards.

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Explorer
Explorer
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Registered: ‎06-09-2015

Re: DPU TRD for ZCU104 ?

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Hello everyone, we have build and tested the "DPU TRD for ZCU104" as the PG338 Guide and Tcl file provided by @jheaton. We also have published an article on it and showed up the results there. Please follow this article [step-by-step tutorial] for implementing "DPU TRD on ZCU104": DPU TRD for ZCU104Here is the "Demo Test -DPU TRD for ZCU104" download link [File size: 141MB] : https://drive.google.com/open?id=1AyxDg1TRwMIcIaAdqrQdf2cvw4Nj0uen . This project also has been tested by @shairva  on the ZCU104 FPGA Board.

Regards,
krishna@logictronix.com

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-21-2008

Re: DPU TRD for ZCU104 ?

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The DPU TRD can be retargeted to the ZCU104 board.

Vivado:

I have attached a script to create the project in 2018.2. Place it in the pl dir and execute vivado -source zcu104.tcl

The main changes were:

1) Changing project part to ZCU104 Evaluation Board.

2) Applying board presets to ZyncUltraScale+ block in IP Integrator.

3) Changing the DPU options to use 20 Ultra Rams. This is needed becuase the device on the ZCU104 has less brams than the device on the ZCU102.

4) Increasing place and route effort levels for Vivado.

Petalinux

You can use the existing zcu102-dpu-trd-v2018.2 bsp for the Petalinux project and follow the TRD instructions. There is one change you have to make:

1) In the petalinux-config step you will need to change the machine name to zcu104-revc: DTG Settings -> MACHINE_NAME = zcu100-revc

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-21-2008

Re: DPU TRD for ZCU104 ?

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Correction:

The last line should be:

1) In the petalinux-config step you will need to change the machine name to zcu104-revc: DTG Settings -> MACHINE_NAME = zcu104-revc

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Contributor
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Registered: ‎09-19-2018

Re: DPU TRD for ZCU104 ?

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I think that file has some hard-coded paths because I'm getting this error:

Can you help me?

 

Captura.PNG

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-21-2008

Re: DPU TRD for ZCU104 ?

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First run the script ./scripts/trd_prj.tcl, this will create a project for the zu102 and will create the file top_wrapper.v

Then run the zcu104 script, this will create a new project for the zcu104. This script will create the project  pl/zcu104, and when this completes you can delete the zcu102 project files in pl/prj.

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Contributor
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Registered: ‎09-19-2018

Re: DPU TRD for ZCU104 ?

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Dear @jheaton ,

I've followed your instructions:

1- Run ./scripts/trd_prj.tcl

2- Run zcu104.tcl

Until here, everything was OK

3- Generate Bitstream <--- Here I got these problems:

Captura.PNG

If we go to the timing report:

Captura1.PNG

What are your recommendations to fix that ?

Thanks in advance

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-21-2008

Re: DPU TRD for ZCU104 ?

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It meets timing in Vivado 2018.2. What versio of Vivado did you use?

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Contributor
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Registered: ‎09-19-2018

Re: DPU TRD for ZCU104 ?

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I'm using Vivado 2018.3

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Observer
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Registered: ‎02-02-2018

Re: DPU TRD for ZCU104 ?

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Dear @jheaton ,

I've installed Vivado 2018.2 and run the synthesis, and I am not meeting the timing constraints.

Can you please help me ?

Captura.PNG

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-21-2008

Re: DPU TRD for ZCU104 ?

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Make sure the Synth Startgey is set to Flow_PerOptimzed_high and the Implemenation tio  Performance_ExporePostRoutePhysOpt. 

Please attach the runme.log file from the impl_1 dir.

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Contributor
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Registered: ‎09-19-2018

Re: DPU TRD for ZCU104 ?

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With Synth Startgey set to Flow_PerOptimzed_high I could not meet the timing constraints at the synthesis, why? do you know that?

But then, using Performance_ExporePostRoutePhysOpt at the implementation, I could meet the timing constraints.

I've used Vivado 2018.2

Captura2jpg.jpg

Thank you

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Contributor
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Registered: ‎09-19-2018

Re: DPU TRD for ZCU104 ?

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@jheaton why it does not meet the timing constraints in Vivado 2018.3 ?

Is there any solution for that?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-21-2008

Re: DPU TRD for ZCU104 ?

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The timing results post Synthesis are using estimated delays for routing based on wire length, and there will be differnces from the final timing post route.

A small negative WNS > - 500ps post Synthesis is generally okay, and often Vivado can still meet timing. A large negative WNS after Sythesis means the design is very unlikely to meet timing and you need to change the design or Sythesis settings. Its also okay to have a  small negative WHS sfter Synthesis as well, the router typiclally fix these hold errors. 

The DPU TRD was tested on Vivado 2018.2 and Petalinux 2018.2. I recommend staying with this version of Vivado, until the next version of the DPU comes.

A new version of the DPU is comming out very soon.

 

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Explorer
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Registered: ‎06-09-2015

Re: DPU TRD for ZCU104 ?

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Hello everyone, we have build and tested the "DPU TRD for ZCU104" as the PG338 Guide and Tcl file provided by @jheaton. We also have published an article on it and showed up the results there. Please follow this article [step-by-step tutorial] for implementing "DPU TRD on ZCU104": DPU TRD for ZCU104Here is the "Demo Test -DPU TRD for ZCU104" download link [File size: 141MB] : https://drive.google.com/open?id=1AyxDg1TRwMIcIaAdqrQdf2cvw4Nj0uen . This project also has been tested by @shairva  on the ZCU104 FPGA Board.

Regards,
krishna@logictronix.com

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Observer
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Registered: ‎04-16-2019

Re: DPU TRD for ZCU104 ?

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Is zcu104.tcl released for DPU1.4 IP?I need it badly.

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Observer
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Registered: ‎04-16-2019

Re: DPU TRD for ZCU104 ?

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If you follow the steps, then vivado generated. HDF files for ZCU104 are not used?

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Participant
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Registered: ‎05-31-2019

Re: DPU TRD for ZCU104 ?

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Thanks for your instruction! Is there a plan to retarget the DPU design to Avnet UltraZad Board? Which is use ZU11EG.

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Adventurer
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Registered: ‎05-27-2019

Re: DPU TRD for ZCU104 ?

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@cumtdaibo wrote:

Thanks for your instruction! Is there a plan to retarget the DPU design to Avnet UltraZad Board? Which is use ZU11EG.


UltraZad ?  Do you mean UltraZed? 

I also want to know how can I transfer a DPU from ZCU102 to other UltraScale MPSoC platform? such as ZU11EG, which @cumtdaibo mentioned above.

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Registered: ‎05-31-2019

Re: DPU TRD for ZCU104 ?

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Not Ultrazed, I mean the UltraZ AD board from AVNET.
捕获.JPG
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Adventurer
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Registered: ‎05-27-2019

Re: DPU TRD for ZCU104 ?

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Hi @cumtdaibo 

I search this topic yesterday, share with you:

Image_20190924-153404.png

and Zynq 7000 family

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Adventurer
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Registered: ‎10-04-2018

Re: DPU TRD for ZCU104 ?

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jheaton,

I'm just a bit confused about where to find the /scripts/trd_prj.tcl file.

I'm set up with the zcu104 board and have downloaded the image for the zcu104 to the SD card and run it. I have also downloaded the zcu104 directory of tools for the Dnndk to the board, and have run some of the demos.

Running Ubuntu 18.04, Vivado, SDK and Petalinux 2018.3. I should therefore have all of the tools that I need.

As others in this thread have tried, I desire to run some of the AI demos which were intended for the zcu102. I downloaded and tried the "vivado -source zcu104.tcl" and have run across the "top_wrapper.v" missing error. 

So, I would run the /scripts/trd_prj.tcl file, but I don't know where to find it.

Thank You

Tom

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Explorer
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Registered: ‎06-09-2015

Re: DPU TRD for ZCU104 ?

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Hello @miner_tom , if you have downloaded "zcu102-dpu-trd-2018-2-190531.zip" from https://www.xilinx.com/products/design-tools/ai-inference/ai-developer-hub.html#edge then you can extract the Zip file. Also download the zcu104.tcl and put it inside the extracted folder as "zcu102-dpu-trd-2018-2-190531/pl".
Now, openup vivado on Windows [similr process will be followed for Linux also], from the Tcl Console of VIVADO you can do "change directory" into the extracted folder.

For example, if you are on Windows and have the extracted zip file at E drive then you may run this command on Tcl console of VIVADO:
"cd E:/zcu102-dpu-trd-2018-2-190531/pl", now you can run the command "source /scripts/trd_prj.tcl". After the project created for ZCU102, goto Tcl Console window of that zcu102 project and do "source zcu104.tcl".

Now you will get the project of name "zcu104" at "cd E:/zcu102-dpu-trd-2018-2-190531/pl". I hope this helps you!

Regards,
krishna@logictronix.com
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Adventurer
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Registered: ‎10-04-2018

Re: DPU TRD for ZCU104 ?

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Thank you so much for the reply to my post. I have been out of town for a couple of days and will try your suggestion as soon as I am able.

Regards
Tom
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Registered: ‎10-04-2018

Re: DPU TRD for ZCU104 ?

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Hi, and your post helped me very much.

However, even with the executing the zcu104.tcl file, the project still "believes" (poor choice of words) that the zynq device is the XCZU9EG which is in the zcu102 development board. The zcu104 uses the  XCZU7EV. 

I purchased the zcu104 and the certificate based license only gives me the ability to do synthesis with the  XCZU7EV. Therefore, after running the zcu104.tcl file I received the following error during synthesis:

[Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xczu9eg'. Please run the Vivado License Manager for assistance in determining
which features and devices are licensed for your system.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ". If you are using a license server, verify that the license server is up and running a version of the xilinx daemon that is compatible with the version of Xilinx software that you are using. Please note that Vivado 2017.3 and later requires upgrading your license server tools to the Flex 11.14.1 tools. Please confirm with your license admin that the correct version of the license server tools are installed.

So, I am a bit confused. I thought that running the script would change the project files such that the DPU projects originally designed for the zcu102 would run on the ZCU104. I don't see how this could be if the project still requires the xczu9eg.

Do you have a suggestion?

Thank you for your help.

Tom

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Registered: ‎12-03-2018

Re: DPU TRD for ZCU104 ?

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Hello,

I want to run the TRD on the ZCU104 from the tcl script you provided.

First I tried to adapt your script for vivado 2019.2 and DPU V3.1.

I managed to synthetize with Flow_PerfOptimized_high as strategy but I obtain congestion issues during the implementation with Performance_ExplorePostRouteOpt as strategy :

[Route 35-3] Design is not routable as its congestion level is 6.
Resolution: Run report_route_status to get a full summary of the design's routing, as it is likely that the design has not been routed at all. To find the areas of the congestion, use the route congestion Metrics in the Device View and check the logfile for the Congestion Report.

I also try in vivado 2018.2 without modifying the zcu104.tcl and I obtain the same kind of problem :

 

DPU_pb1.PNG

 

DPU_pb2.PNG

I know I can modify the DPU parameters i order to reduce ressources and then avoid routing congestion but did I miss something with the script ?

Thank you for your help,

Matthieu

DPU_pb2.PNG
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Re: DPU TRD for ZCU104 ?

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Hello @matthieu_elsys , how many DPU core are you using on VIVADO 2019.2 design? Have you utilized this strategies?
Before synthesis use it from Tcl console: set_property strategy "Flow_PerfOptimized_high" [get_runs synth_1]

After synthesis and before implementation started, use these: set _property strategy “Performance_ExplorePostPhysOpt” [get_runs impl_1] and set_param place.runPartPlacer 0 

And have you use DPU 3.1 also in VIVADO 2018.2 TRD design? or the older DPU IP (version 2.0)?

Regards,
krishna@logictronix.com
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Registered: ‎12-03-2018

Re: DPU TRD for ZCU104 ?

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Hello,

Thank you for your Answer :

  • "how many DPU core are you using on VIVADO 2019.2 design?"
    • I use two DPU core
  • "Have you utilized this strategies? Flow_PerfOptimized_high & Performance_ExplorePostPhysOpt"
    • Yes
  • "And have you use DPU 3.1 also in VIVADO 2018.2 TRD design? or the older DPU IP (version 2.0)?"
    • In Vivado 2018.2 I used DPU 2.0
    • In Vivado 2019.2 I used DPU 3.1
    • In both I had routing issues (with zcu104.tcl configuration)

I Finally managed to fit the DPU 3.1 (with 2 cores) into the ZCU 104 in vivado by disabling :

  • Channel augmentation
  • DepthwiseConv
  • Average pooling

 

 

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