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Observer
Observer
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Registered: ‎02-21-2019

AXI DMA SG

Hello,When I use AXI-DMA SG mode, when I write 0x200 to the CONTROL (0x18) register in BD, the value of the STATUS (0x1c) register is always 0x8C000100. What is this? Moreover, only 0x100 valid data is received in the buffer address, and all subsequent numbers are 0. Please help me!

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Moderator
Moderator
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Registered: ‎01-09-2019

Hello @liulei 

Which channel are you running the DMA, a transmit or receive buffer?  The Status register description can be found on pag 47-48 of PG021 for the S2MM side (https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf).

Since you have a value in bits 26-27 I am going to guess you are transferring S2MM.  That value for the Status register indicates the BD has completed its transfer (0x8), that BD was both the SOF and EOF (0xC), and you transferred 0x100 bytes of data.

Can you provide a waveform of what you are seeing with the transfer of data, and when you are setting the value 0x200 to the Control register?  Are you sure that the value 0x200 is being written to the Control register for that specific transaction?

At any time is the Status register showing any other bits asserted in the upper byte besides 0x8Cdd..dd)?

Does your BD have adequate space to transfer 0x200 bytes of data?

Thanks,
Caleb
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Observer
Observer
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Registered: ‎02-21-2019

I use PL->PS channel, SG mode, cycle mode, each BD's buffer length is set to 0x200, but the actual received only 0x100 valid data, after RxSetup view BD information, length is 0x200, But the status is 0x0x8C000100

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Moderator
Moderator
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Registered: ‎01-09-2019

@liulei 

A waveform of the simulation or an ILA if running in hardware would be very useful.

One note is if you are using cyclic mode, are you being careful to deal with the completed bit properly?  The cyclic mode ignores the completed bit and continues on without worrying about whether the BD was used before/completed.  In our example code this is handled by clearing the completed bit after every transfer.

A SG cyclic mode example can be found here: https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sgcyclic_intr.c

It also might be worthwhile to start by using that code, and then altering to fit the size of the transfer/BDs you want.

Thanks,
Caleb
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Observer
Observer
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Registered: ‎02-21-2019

The buffer length of each BD configured on the PS side is 4096, and the packet length sent by the PL side is 2048. Then, will 2 packets be received in one BD? From the point of view of the phenomenon, only one packet will be received in each BD buffer, and the next packet will store data from the buffer base address of the next BD. Why?

 

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Moderator
Moderator
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Registered: ‎01-09-2019

@liulei

By the buffer length on the PS side, you are talking about how large your software configures that particular BD to be, is that correct?  And then what you say is the packet length is how much data is sent to the DMA from your custom IP that you want to DMA somewhere else, is that also correct?

I am not quite sure what that register dump is saying and what is being highlighted in that image, can you clarify a little more for me?

Have you been able to compare with the example Cyclic SG driver to your code?  Does that provide any clarity to your issue?

To your question about the packet length of the BD, if you provide the BD with only 2048 bytes of data and then say it is complete then there should only be 2048 bytes that are transferred.  Same would be true of providing 4096 bytes and setting the complete bit.

Thanks,
Caleb
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