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hagaya
Visitor
Visitor
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Registered: ‎12-10-2018

AXI Interconnect and AXI VIP

Hi,

I running simulation on Questa with the following configuration : 2xVIP (as Masters) , Interconnect (2 Master and 2 Slave) , 2xAxi Slave MM

First thing i see i that the interface of the S00 which is connected to one of the VIP is missing with ID signals(AWID, BID...).

All the other interfaces have the ID signals. The problem is that i can't connect the write response back to the vip because it's missing the ports.

In addition i get the following error : "AXI4_ERRS_BRESP_AW" : A slave must not give a write response before the write address. This error ocures several clocks before the actually BVALID arrives and i guess it thinks it is a response for a new transaction.

Please advice

Hagay

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florentw
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1,386 Views
Registered: ‎11-09-2015


@hagaya wrote:

Hi,

I running simulation on Questa with the following configuration : 2xVIP (as Masters) , Interconnect (2 Master and 2 Slave) , 2xAxi Slave MM

First thing i see i that the interface of the S00 which is connected to one of the VIP is missing with ID signals(AWID, BID...).

[Florent] - Note that the ID is optionnal on the AXI4 interface.This will depend on the interfaces configuration. Check the VIP you should be able to force it to have the ID interface.

Also it will not be present if the interface is AXI4-Lite.

All the other interfaces have the ID signals. The problem is that i can't connect the write response back to the vip because it's missing the ports.

In addition i get the following error : "AXI4_ERRS_BRESP_AW" : A slave must not give a write response before the write address. This error ocures several clocks before the actually BVALID arrives and i guess it thinks it is a response for a new transaction.

[Florent]  - Can you share the full waveform? Also you should see the simulation time in the log. Could you show the waveform at this specific time?

Please advice

Hagay


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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dgisselq
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Registered: ‎05-21-2015

@hagaya,

I've been building and testing a variety of AXI formal verification IP products.  Along the way, I've discovered two common mistakes in the cores I've verified:

  1. There's a tendency to check for VALID & READY & something else.  This often leads to dropped transactions.  I discuss this in a blog article here.
  2. The second common mistake is associated with the AxLEN field present in AXI but not AXI-lite.  This field is off-by-one from the actual length to be transferred.  As a result, if you want to request a single read or write you need to set AxLEN to 0 and not to one.  I know I've discussed this on twitter recently, but don't seem to have the image I posted there handy.

Some resources you might find valuable in debugging your code include 1) using a different (open-source) AXI interconnect, 2) a bus fault isolator that will detect a fault in your code and trigger the ILA (Vivado has one in their IP generator, although I've never tried it), 3) A high performance AXI-lite to AXI bridge which can simplify your AXI transactions at the cost of two clocks of latency, 4) If your master isn't driving the ID  signals, or not driving wide enough ID signals, then feel free to just set any AxID signals to zero.  You should then set the VIP ID signals to zero with no loss of fidelity, assuming everything else works.  Alternatively, you'll find that formal verification, such as with SymbiYosys, is often easier to use and can find more bugs than your typical/traditional AXI Verification IP.

Dan

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