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Visitor
Visitor
985 Views
Registered: ‎05-31-2018

AXI Lite Verification Example

Hi there, I tried to run an example project on Vivado 2017.1 Webpack edition. I found that example on this website https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842507/Using+the+AXI4+VIP+as+a+master+to+read+and+write+to+an+AXI4-Lite+slave+interface. I did exactly what it says but it didn't work and I can't find out the reason. Here is my simulation code and block diagram.

import axi_vip_v1_0_1_pkg::*;
import design_1_axi_vip_0_0_pkg::*;

module bram_test();

bit                     aclk = 0;
bit                     aresetn=0, aresetn_0=0;
xil_axi_ulong 	        addr1=32'hC0000000, addr2 = 32'hC0000004;
xil_axi_prot_t          prot = 0;
bit [31:0] 	            data_wr1=32'h01234567,data_wr2=32'h89ABCDEF;
bit [31:0] 	            data_rd1,data_rd2;
xil_axi_resp_t 	        resp;

always #5ns aclk =   ~aclk;

design_1_wrapper DUT
(
    .sys_clock(aclk),
    .reset_rtl(aresetn),
    .reset_rtl_0(aresetn_0)
);

// Declare agent
design_1_axi_vip_0_0_mst_t      mst_agent;

// Transaction method
//task wr_tran();
//    axi_transaction  wr_transaction;
//    wr_transaction   = mst_agent.wr_driver.create_transaction("write transaction");
//    WR_TRANSACTION_FAIL: assert(wr_transaction.randomize());
//    mst_agent.wr_driver.send(wr_transaction);
//endtask

//task rd_tran();
//    axi_transaction  rd_transaction;
//    rd_transaction   = mst_agent.rd_driver.create_transaction("read transaction");
//    RD_TRANSACTION_FAIL_1a:assert(rd_transaction.randomize());
//    mst_agent.rd_driver.send(rd_transaction);
//endtask

initial begin
    
    #50ns
    aresetn = 1;
    aresetn_0 = 1;
    
    fork
        //Create an agent
        mst_agent = new("master vip agent",DUT.design_1_i.axi_vip_0.inst.IF);
     
        // set tag for agents for easy debug
        mst_agent.set_agent_tag("Master VIP");
     
        // set print out verbosity level.
        mst_agent.set_verbosity(400);
     
        //Start the agent
        mst_agent.start_master();
    join_none
//        wr_tran();
//        #1000ns
        
//        rd_tran();
//        #1000ns
        
        #20ns
        mst_agent.AXI4LITE_WRITE_BURST(addr1,prot,data_wr1,resp);
        
        #20ns
        mst_agent.AXI4LITE_WRITE_BURST(addr2,prot,data_wr2,resp);
        
        #70ns
        mst_agent.AXI4LITE_READ_BURST(addr1,prot,data_rd1,resp);
        
        #20ns
        mst_agent.AXI4LITE_READ_BURST(addr2,prot,data_rd2,resp);
        
        #200ns
        if((data_wr1 == data_rd1)&&(data_wr2 == data_rd2))
            $display("Data match, test succeeded");
        else
            $display("Data do not match, test failed");
    
        $finish;
    
end

endmodule

Capture.PNGI just use BRAM and Master AXI4Lite Verification IPs, others come with "run connection automation".  

 

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Xilinx Employee
Xilinx Employee
935 Views
Registered: ‎10-04-2016

Hi @sya0,

When you say your simulation doesn't work, what is the failure?

Is the base address for your BRAM 0xC000_0000?

Regards,

Deanna

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