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Adventurer
Adventurer
459 Views
Registered: ‎10-29-2018

AXI Traffic generator in Master Loopback mode without Processor intervention

Dear Sir,

I am simulating AXI Traffic Generator in Master Loopback mode without PS intervention. I have connected M_AXIS_MASTER to S_AXIS_MASTER. I have given the appropriate signal to clk and reset port. I have generated a high pulse at core_ext_stop and core_ext_start port. When I simulate the design, axis_err_count port is 0000. 

To check whether axis_err_count port is counting no. of errors properly, I corrupted the m_axis_1_tdata as follows and, then fed to s_axis_1_tdata:

assign s_axis_1_tdata_c = m_axis_1_tdata + 32'd10;

Still s_axis_err_count is 0000. Please suggest how to resolve this issue.

Further, I brought up all AXI stream data interface signal to the top Verilog module as port, then I simulated the design. I observed following in the simulation result:

1. m_axis_1_tvalid and s_axis_1_tready is never high. Please see below the attachment.  

Please help me out to sort the above issue.

Any help would be appreciated.

Thank you and Regards,

Puja Kumari

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1 Reply
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Scholar
Scholar
440 Views
Registered: ‎03-28-2016

I would investigate why the s_axis_1_tready signal is a "Z".  As a test, you could try forcing m_axis_1_tready to be a "1"

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com