AXI Traffic generator in Master Loopback mode without Processor intervention
I am simulating AXI Traffic GeneratorinMaster Loopback mode without PS intervention. I have connected M_AXIS_MASTER to S_AXIS_MASTER. I have given the appropriate signal to clk and reset port. I have generated a high pulse at core_ext_stop and core_ext_start port. When I simulate the design, axis_err_count port is 0000.
To check whether axis_err_count port is counting no. of errors properly, I corrupted the m_axis_1_tdata as follows and, then fed to s_axis_1_tdata: