04-04-2018 05:59 AM
I made a custom AXI Master IP using the example code that was generated after creating AXI Peripheral ( Tools -> Create and Package New IP -> Create AXI4 Peripheral ).
One of the changes I made was having Read Data Width 512 bits and Write Data Width 256 bits (notice the different data widths).
The custom IP is connected to 7 series MIG and two AXI BRAM controllers via an AXI SmartConnect. The custom IP reads from MIG and one of the BRAMs and writes to the other BRAM. The reads are being done properly.
I used System ILA to debug the AXI transactions on both sides of AXI SmartConnect. I observed the following
One way is to make both read and write data widths equal. I'm looking for other possible solutions.
I've faced this issue when using AXI Interconnect as well.
Please suggest ways to solve this problem.
04-04-2018 10:34 PM - edited 04-04-2018 10:35 PM