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Adventurer
Adventurer
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Registered: ‎08-10-2017

All Zeros at alternate AXI Narrow Burst Write transaction

I made a custom AXI Master IP using the example code that was generated after creating AXI Peripheral ( Tools -> Create and Package New IP -> Create AXI4 Peripheral ).
One of the changes I made was having Read Data Width 512 bits and Write Data Width 256 bits (notice the different data widths).

 

The custom IP is connected to 7 series MIG and two AXI BRAM controllers via an AXI SmartConnect. The custom IP reads from MIG and one of the BRAMs and writes to the other BRAM. The reads are being done properly.

 

I used System ILA to debug the AXI transactions on both sides of AXI SmartConnect. I observed the following

  1. On the customer IP - SmartConnect side, the M_AXI_WDATA signal is of 512 bit (even though I explicitly declared it as 256 bit). The higher 256 bits are all zeros and the lower 256 bits contained valid data. AXI Smartconnect is probably considering write transaction as narrow burst. (Refer attachment IP_SMC.ila)
  2. On the SmartConnect - AXI BRAM side, WDATA of alternate transaction is all zeros (i.e at every odd-numbered transaction, valid data is being written to BRAM and at every even-numbered transaction, zeros are being written to BRAM). This is the problem I'm facing. (Refer attachment SMC_WriteBRAM.ila)

 

One way is to make both read and write data widths equal. I'm looking for other possible solutions.

I've faced this issue when using AXI Interconnect as well.

 

Please suggest ways to solve this problem.

 

 

Thank you

 

Jagannath

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Adventurer
Adventurer
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Registered: ‎08-10-2017

The waveforms in IP_SMC.ila clearly shows that WSTRB is 0x00000000ffffffff. This means the lower 256 bits (32 bytes) of WDATA are valid in every write transaction. But I can't seem to figure out why zeros are being written in alternate transaction.
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