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Observer
Observer
514 Views
Registered: ‎11-09-2018

Axi Simple DMA wait

Hi All,

 

I am using the zedboard and sdsoc to interface with the FPGA for a project. 

I currently my application uses data flow and hls streams in between each module. 

Currently my application hangs in DMA wait loop and I am stumped as to how to debug this issue. 

In HLS I have confirmed that each application is reading and writing to and from streams the correct number of times. My first thought was that one application was stuck in a blocking read and caused this issue but unfortunately that is not the case. 

Has anyone had these issues and can post what they did to resolve? Or even some things to look at or consider?

Thanks!

 

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2 Replies
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Newbie
Newbie
489 Views
Registered: ‎12-02-2018

Hi Eric,

We are also having the same issue. Ping us if you were able to get anywhere with this query!

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Observer
Observer
424 Views
Registered: ‎11-09-2018

Hi @hale2bopp,

I solved this issue a couple times. I think the main issue is that our stream depth was not appropriate. I made one of my streams have a shallow depth because I thought it was processing at a certain speed but I guess it was not. I never worked out the deadlock scenario. but both read and write are blocking. My suspicion was some process tried to write to a full stream got blocked, while another stream got blocked reading from an empty stream waiting for data. In my application I could never work out the conditions to get this scenario to replay but when increasing the stream depth the deadlock was resolved. Another weird observation I made was that if you have an output buffer we need to write atleast a byte to it.

 

For example If I had a top level

Top(uint8_t input[100], uint8_t output[100)

{

hls::stream strm

function1(input,strm);

function2(strm,output); <--- you need to write a byte to output... do know why but it worked for some reason...

}

 

Hopefully this makes sense if it does not maybe I can try again (:

 

Eric

 

 

 

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