11-29-2018 07:36 AM
I want to send buffer from PS app to FIFO in PL side via AXI lite bus?
Is there any idea how this is done?
How do I know when a new data appeared on PL side?
12-10-2018 02:50 PM
Which FIFO IP are you targeting?
Generally speaking, the FIFO should have a memory mapped address location in the PL. This address will depend on which PS-PL AXI Master Port the FIFO connects to. You need to consult the Address Editor in IP Integrator to find the base address for the FIFO.
Depending on which FIFO IP you are attempting to write to, you might need to add an offset to the base address of the FIFO.
How to determine whether there is data in your FIFO depends on the IP. Some have an empty signal that will de-assert when there is data present in the FIFO. Others might have a memory mapped register that software can query to see the condition of the FIFO.
12-20-2018 02:07 AM
I suggest to use an AXI-Stream FIFO and only enable the Transmit Data channel.
When there is data available the AXI-Stream tvalid will indicate this.