05-23-2018 12:02 PM - edited 05-30-2018 10:01 AM
I am converting a working Zynq UltraSCALE+ design to use SmartConnects instead of AXI interconnects. In Vivado 2017.4, the process of replacing interconnects with SmartConnects has been simple and everything "just works". However, there is one problem where the 'AXI 1G/2.5G Ethernet Subsystem' IP causes the PetaLinux ethernet driver to hang when a SmartConnect is used on the AXI Lite interface. Trial and error shows that placing an 'AXI Clock Converter' IP between the SmartConnect and the ethernet IP fixes the system hang. There is only one clock input to the SmartConnect and the Clock Converter is silly since both the master and slave interface are driven by the same clock.
Screenshot of the Block Design is attached. Any idea what is going on here? Is there a bug with the Xilinx Ethernet IP interfacing with SmartConnect?
05-25-2018 03:53 PM
It looks like a bug in the 'AXI 1G/2.5G Ethernet Subsystem' IP is to blame. An ILA capture of the AXI bus during the "ifconfig eth1 up" command shows the hang is because there is no response to the write of register 0x40C XAE_FCC_OFFSET during the axienet_device_reset() function in the driver (line 944).
Probably because the ethernet IP asserted AWREADY and WREADY one cycle too soon before it had sent the BVALID response for the previous write. You can see in the screenshot below the AW_CNT and B_CNT = 2 for a clock cycle and then get stuck at 1 forever after. Presumably the reason the bug does not show up with AXI Interconnect is that SmartConnect has different timing, providing the 2nd address immediately after the 1st address is consumed.
12-05-2018 03:45 AM
I am facing a similar issue. Where can we find the description of AXI ILA signals (AW_CNT, B_CNT, AR_CNT, R_CNT) signals and meaning of opcodes 1,2,3 for these signals.
Please share the link of the document.
Thanks & Regards
12-05-2018 04:54 AM
I am initiating one AXI write transaction from the Zynq Ultrascale MPSoC processor. I am using custom interconnect and custom AXI 4 Slave. The transaction completes with OKAY response, but Zynq processor throws an exception. AW_CNT and B_CNT are stuck at 1. B_CNT is at 3 for 1 clock and then goes to 1.
Is the Zynq processor timing out. What does B_CNT = 3 signify. Please find below AXI ILA capture for this transaction
Thanks & Regards