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Visitor eonishi
Registered: ‎11-10-2018

Some ADC values appear to be missing using the AXI4 stream interface

The chart data represents the sampled data from the AXI4 stream output (xadc IP logic).  My ARB is set to 20khz ~ 0 to 1 volt in amplitude.  The capture frequency and amplitude are representative of the injected signal.  The values that are missing are actually stored in the DMA as '0'.  I could understand if the sine wave was distorted horizontally, but shouldn't the m_axis_tvalid hold back the data if it's not ready?  

*Edit it's actually 0.8 MSPS




 And at 500 Hz




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Scholar jg_bds
Registered: ‎02-01-2013

Re: Some ADC values appear to be missing using the AXI4 stream interface

TREADY (not TVALID) can be used by an AXIS slave to hold-back a transfer of data from a master. Many masters, however, contain little or no buffering, so they do not support TREADY back-pressure. (e.g. look at the Rx stream of a Xilinx AXI TEMAC.) As such, if data is not captured by a slave when the master asserts TVALID, the data is gently placed in the bit bucket.

-Joe G.