11-13-2018 05:33 AM
on the Xilinx wiki page 'Using the AXI4 VIP as a master to read and write to an AXI4-Lite slave interface' I can read :
-> I understand that the simulation source that instantiates, initializes and exercises the AXI VIP needs to be in SystemVerilog.
however, I have many testbenches that were written in VHDL. So far I used a VHDL based (open source) BFM, which was added as a few VHDL source files, and instantiated and connected to my DUT in the VHDL testbench. It provided me with simple axi_write and axi_read commands to exercise my custom axi4-lite ip.
Instead of re-writing all my testbenches in VHDL / learning SystemVerilog (not much time at the moment), I want to know if I can somehow use the AXI VIP in my VHDL testbenches. I basically need these 2 types of functions in my VHDL testbench :
do I need to create some 'wrapper' code around the Systemverilog file (like the one described on the wiki page above) that instantiates and controls the VIP? That SystemVerilog file now instantiates the DUT, but I think I need to do this in my VHDL top level file in that case.
in short, I'm puzzled on how to integrate the AXI VIP with VHDL testbenches... any example on this?
11-13-2018 07:15 AM - edited 11-13-2018 07:17 AM
I would try to build a VHDL wrapper around the SV VIP.
Fundamentally the top level VIP in SV, whether master or slave, will have the interface signals such as
logic [31:0] awaddr;
which converts to signal awaddr : std_logic_vector (31 downto 0);
This is just an idea, I don't know how difficult will this be or is it feasible at all. I think it is better to try for a couple of days than paying for a VHDL based VIP or spending some man-days on understanding the basics of SV.
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11-20-2018 09:00 AM - edited 11-20-2018 09:04 AM
I have been able to get the AXI VIP working with SystemVerilog by following Xilinx documentation and online examples, however when I integrate this SystemVerilog file into a top-level vhdl file, then I get an error "ERROR: [XSIM 43-3241] File /wrk/2017.2/nightly/2017_06_15_1909853/packages/customer/vivado/data/ip/xilinx/axi_vip_v1_0/hdl/axi_vip_v1_0_vl_rfs.sv, Line Num 15356, Node ACLK is not annotated."
I found this forum post which seems to be the same issue: Elaboration Error: Node ACLK is not annotated.
Now, we really want to use vhdl as the top level because that is what we use throughout the company for design and simulation. We hoped using the SystemVerilog layer as an intermediate layer to accept triggers from our top-level vhdl testbench.
Our SystemVerilog file:
import axi_vip_v1_0_2_pkg::*; import design_1_axi_vip_0_0_pkg::*; module tb_sysverilog ( input logic aclk_vhdl, aresetn_vhdl ); // Declarations and initialisations xil_axi_ulong addr1 = 32'hC0000000; xil_axi_ulong addr2 = 32'hC0000004; xil_axi_prot_t prot = 0; xil_axi_resp_t resp; bit [31:0] data_wr1 = 32'h01234567; bit [31:0] data_wr2 = 32'h89ABCDEF; bit [31:0] data_rd1; bit [31:0] data_rd2; // Instantiate the device under test design_1_wrapper DUT_wrapped_bd ( .aclk (aclk_vhdl), .aresetn (aresetn_vhdl) ); // Declare agent design_1_axi_vip_0_0_mst_t master_agent; initial begin //Create an agent master_agent = new("master vip agent",DUT_wrapped_bd.design_1_i.axi_vip_0.inst.IF); // set tag for agents for easy debug master_agent.set_agent_tag("Master VIP"); // set print out verbosity level. master_agent.set_verbosity(400); //Start the agent master_agent.start_master(); #70ns master_agent.AXI4LITE_WRITE_BURST(addr1,prot,data_wr1,resp); #20ns master_agent.AXI4LITE_WRITE_BURST(addr2,prot,data_wr2,resp); #70ns master_agent.AXI4LITE_READ_BURST(addr1,prot,data_rd1,resp); #20ns master_agent.AXI4LITE_READ_BURST(addr2,prot,data_rd2,resp); #200ns if((data_wr1 == data_rd1)&&(data_wr2 == data_rd2)) $display("Data match, test succeeded"); else $display("Data do not match, test failed"); $finish; end endmodule
And top-level VHDL file:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity tb_vhdl is end tb_vhdl; architecture tb of tb_vhdl is -- Constants --- constant AXI_ACLK_period : time := 10 ns; -- 100MHz -- Signals --- signal AXI_ACLK : std_logic; signal AXI_ARESETN : std_logic; signal sim_end : boolean := false; -- Verilog components --- component tb_sysverilog2 port ( aclk_vhdl : in std_logic; aresetn_vhdl : in std_logic ); end component; -- testbench --- begin --- DUT --- tb_sysverilog_i : tb_sysverilog2 port map ( aclk_vhdl => AXI_ACLK, aresetn_vhdl => AXI_ARESETN ); --- clock process --- axi_clk_gen : process begin while (not sim_end) loop AXI_ACLK <= '0'; wait for AXI_ACLK_period / 2; AXI_ACLK <= '1'; wait for AXI_ACLK_period / 2; end loop; wait; end process axi_clk_gen; --- test sequence --- process begin --- 1) reset AXI_ARESETN <= '0'; wait for 50 ns; AXI_ARESETN <= '1'; -- 2) run for 500 ns --- wait for 500 ns; sim_end <= true; end process; end tb;
12-10-2018 06:13 AM
I had some partial success by adding a system verilog wrapper on top of my VHDL simulation top. With that arrangement, I could issue some read and write transaction, but not access the sparse memory model of a zynq-7000. You can have a look at https://forums.xilinx.com/t5/Simulation-and-Verification/read-mem-does-not-see-axi-write-done-on-HP0-on-the-Zynq-7000-VIP/m-p/907090#M24061
This being said, I converted my design hierarchy to bring the block design as close to the top as possible and I use a single very simple system-verilog testbench and put all the logic in submodule or side-module and it works.
03-14-2019 02:53 AM
Thanks, your link contains some good information for us on how to proceed.