02-26-2018 02:14 PM
Im tring to use the AXI DMA , for now in a mode named SIMPLE DMA, that just transfer data with source/destination inside DDR
Setting the IP in SDK via C code seems easy , but debug is not working (debug dont stop to main ).
So, before ask why, I would like to know if the block desig I create is correct.
Syntesis up to bitstream are created, and hw is exported to SDK.
In attach the Block Desing i created.
Thanks for your time
02-26-2018 02:48 PM - edited 02-26-2018 02:52 PM
your block design looks ok - typically you would put an AXI4 Stream data fifo between the mm2s and s2mm, so it can capture at least single 'packet'
AR# 57550 Example Designs - Designing with the AXI DMA core
AR# 57561 - Example Design - Using the AXI DMA in polled mode to transfer data to memory
02-27-2018 08:32 AM
Thanks for reply
Looking at other schematic was very intresting.
The problem with debug is again present. I used the more simple axi dma project (that with polling)
for chk if a empthy application in c will debug (so the dma will not operate because not initialized by
a code). So i did:
- open the project (the more simple is using the polling) , and generate the bitstream
-export the HW
-open the sdk
-create the bsp
-create a hello word app
-set the system debugger
-launch debug and wait it stop to main()
And it dont stop.
Using other project different than this, and more simple (example with some custom ip ), the debug work.
So seems my schematic with dma, and also one schematic you supply to me via previous link, give this debug problem
Thanks for help and axcuse for long mail
02-28-2018 01:18 AM
What is the output of the debugger? Any error message that can help? Can you upload the sdk.log file here?
I checked your schematic again, and what's strange is that you have 2 different clocks : FCLK0 and FCLK1, you also have 2 reset blocks. Try to start over with your block design from scratch, and work with only FCLK0 and 1 reset block. For your simple test, it's better to use only 1 clock.
02-28-2018 05:55 AM
Thanks for reply
The block design Im using is coming from the first example you provide in previos link...In attach is the schematic in pdf.
The sdk.log is also in attach...no errror i can see in sdk or in log...Simply it dont stop to main .
The c programm is almost empthy..is the default created by sdk, the heloword.....My intention is to write some
config sw after the debug work...
The way I created BSP and debug( System Debug) is he same for other project ,and they work.
Thanks for your time.
03-01-2018 05:34 AM
strange - think your block design looks ok - also you're only printing a helloworld, so you don't access any of the PL hardware so far.
not 100% sure, but looks like it has to do with your debug configuration :
can you try to right-clik on your application -> File -> debug as -> launch on hardware (system debugger). That should stop your debugger at the first line in 'main'. This is the default behaviour.
If you create your own debug session, you could break it at the very first instruction (so not main, but at _vector_table (@0x100000) ), and step from there to see what goes wrong :
03-04-2018 11:41 AM
Thanks for reply Mr Ronny
It stop at entry point 1000 0000h ,and I can step some instruction,but I havo no knowledge how to find some porblem
looking at assembler...I can step up to address 4h:
00000004: stclvc p4, c0, [r10, #-376]
and then, here stop...No more possible to step or run...
In the Register tab, i can see that:
-c0 have empthy value
-p4 i cant find
Could be possible you send me a .xpr project with axi dma, so I will create bitstream and sdk ?
Thanks again for your time
03-16-2018 04:32 AM
I have no news about this problem.
We could try this solution:
- I can send you my DMA project (very simple and poor ) and you try if you have the same debug problem
-you send my your DMA project, and I try with my debug.
For now, all what I find on internet about AXI DMA, put my debug in problem.