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725 Views
Registered: ‎05-09-2018

AXI Multichannel DMA and several Ethernet subsystem cores

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Hello everyone.

I am considering to use the AXI Multichannel DMA (MCDMA) [1] to implement a design with several 1G/2.5G Ethernet subsystem [2] cores. The latter have two additional AXI-Stream buses for carrying status and control information. I have reviewed [1] and, in the page 5, the feature summary includes the following:

"Optional AXI Control and Status Streams to interface to the AXI Ethernet IP. Provides optional Control Stream for MM2S Channel and Status Stream for the S2MM channel to offload low-bandwidth control and status from the high-bandwidth datapath"

I understand that if I configure the MCDMA to use more than one channel, AXI-Stream status and control buses should appear for each one of them. Nevertheless, the MCDMA only exports two AXI-Stream buses no matter how many channels I specify.

Is this a bug of the MCDMA IP core or is this the expected behavior? What should it be the proper way to connect several instances of 1G/2.5G Ethernet subsystem to a single instance of MCDMA?

Thanks for your support,

Best Regards,

Miguel J.

[1]: https://www.xilinx.com/support/documentation/ip_documentation/axi_mcdma/v1_0/pg288-axi-mcdma.pdf

[2]: https://www.xilinx.com/support/documentation/ip_documentation/axi_ethernet/v7_1/pg138-axi-ethernet.pdf

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Xilinx Employee
Xilinx Employee
416 Views
Registered: ‎10-04-2016

Re: AXI Multichannel DMA and several Ethernet subsystem cores

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Hi @miguel.jimenez,

I confirmed with the designers that my understanding of the relationship between M_AXIS_MM2S and the control stream and S_AXIS_S2MM and the status stream is correct.

The timing relationship isn't very strict on the streams. On the S2MM/status side, PG288 says "the status stream should come at the start of the S2MM data stream. If the RxLength In Status Stream is disabled, the status stream can come at any tie during the course of the S2MM frame." (See page 62.) The Packet Filter could operate such that it doesn't allow a data stream to arbitrate for access to the MCDMA until the corresponding status stream has arrived.

On the MM2S/control side, PG288 says "The control associated with the MM2S primary data stream can be sent out of AXI MCDMA prior to, during or after the primary data packet." (See page 61.) It would be up to the packet filter to throttle these streams until both data and control are available.

Regards,

Deanna

 

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6 Replies
Xilinx Employee
Xilinx Employee
521 Views
Registered: ‎10-04-2016

Re: AXI Multichannel DMA and several Ethernet subsystem cores

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Hi @miguel.jimenez,

The AXI Multichannel DMA is really multi-channel in the register programming sense. The 16 channels share M_AXI_MM2S, M_AXI_S2MM, S_AXIS_S2MM and M_AXIS_MM2S interfaces.

The streaming interfaces distinguish which channel a stream is destined for/coming from using the TDEST field in the protocol. This is mentioned on page 7 of PG233 and further elaborated upon in the Typical System case discussed on page 63.

Regards,

Deanna

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505 Views
Registered: ‎05-09-2018

Re: AXI Multichannel DMA and several Ethernet subsystem cores

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Hi @demarco,

You are right, there is only one interface and the TDEST is used for routing purpose. However, it is not the same for Control and Status ports.

I have elaborated a picture to explain you the target design I have to get.

I want to connect several Ethernet subsystems to the Zynq processor using a single instance of an AXI Multichannel DMA (MCDMA) IP core. The Tx and Rx data interfaces can be connected using AXI-Stream Interconnect IP cores that route each transaction depending on its TDEST. However, each Ethernet subsystem module also requires two additional interfaces known as Status and Control streams. In the documentation of the MCDMA IP specifies that it can be configure to export these interfaces. However, it only provides two single interfaces without the TDEST information. Then, it seems that they are global interfaces that are not related to any specific channel.

So, my question is: "Is it the expected behavior?", I mean I do not understand properly what is the utility of these Stream and Control interfaces if they are not associated to a specific channel somehow. I think that TDEST information have been missed for these ones.

And, the final question, "What is the proper way to interconnect two or more Ethernet Subsystem cores using the MCDMA IP core?".

Thanks in advance for your support.

Best Regards.

Miguel J.

 

axi_mcdma_design.png
axi_mcdma_config.png
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Xilinx Employee
Xilinx Employee
458 Views
Registered: ‎10-04-2016

Re: AXI Multichannel DMA and several Ethernet subsystem cores

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Hi @miguel.jimenez,

I am confirming with the designers whether the following is true:

Consider the S2MM path and the status stream: the AXI MCDMA assumes that the data coming in on status stream belongs to the same channel specified by TDEST on the S_AXIS_S2MM interface.

Similarly, on the MM2S path: when the AXI MCDMA sends data on the control stream interface, that data belongs to the same channel specified by TDEST on the M_AXIS_MM2S interface.

The reason I believe these statements to be true is that the only way to close out an S2MM transfer and update the final descriptor is to have the information from the Status Stream. Similarly, the control data comes from the descriptor for the MM2S transfer.

Xilinx does not offer what PG288 refers to as a "packet filter" IP. This is a user-implemented block. That said, the AXI-Stream infrastructure building blocks documented in PG085 might be helpful in developing the packet filter.

https://www.xilinx.com/support/documentation/ip_documentation/axis_infrastructure_ip_suite/v1_1/pg085-axi4stream-infrastructure.pdf

Regards,

Deanna

 

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424 Views
Registered: ‎05-09-2018

Re: AXI Multichannel DMA and several Ethernet subsystem cores

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Hello @demarco,

Thanks you for your fast answer. Please, get back to me when you receive the information from designers, just to be sure that your idea is right.

However, I have an additional question. Let's suppose that you are right and the Control Stream interface is associated to the MM2S channel. Consequently, and as you said, the TDEST information are shared for both of them. Then... What is the timing relationship between Control Stream and MM2S channels? I mean, is the DMA generating at the same time? or one before the other? It is a important restriction to design the Packet filter core you commented.

In addition, I would like to know the same thing for Status Stream interface and S2MM channel.

Thank you again for your support.

Regards,

Miguel J.

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Xilinx Employee
Xilinx Employee
417 Views
Registered: ‎10-04-2016

Re: AXI Multichannel DMA and several Ethernet subsystem cores

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Hi @miguel.jimenez,

I confirmed with the designers that my understanding of the relationship between M_AXIS_MM2S and the control stream and S_AXIS_S2MM and the status stream is correct.

The timing relationship isn't very strict on the streams. On the S2MM/status side, PG288 says "the status stream should come at the start of the S2MM data stream. If the RxLength In Status Stream is disabled, the status stream can come at any tie during the course of the S2MM frame." (See page 62.) The Packet Filter could operate such that it doesn't allow a data stream to arbitrate for access to the MCDMA until the corresponding status stream has arrived.

On the MM2S/control side, PG288 says "The control associated with the MM2S primary data stream can be sent out of AXI MCDMA prior to, during or after the primary data packet." (See page 61.) It would be up to the packet filter to throttle these streams until both data and control are available.

Regards,

Deanna

 

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408 Views
Registered: ‎05-09-2018

Re: AXI Multichannel DMA and several Ethernet subsystem cores

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Hello @demarco,

Thanks for these information, I think I understand properly the AXI Multichannel DMA (MCDMA) IP core. Therefore, I will be able to implement properly the Packet Filter module.

I am going to mark your answer as solution.

Regards,

Miguel J.

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