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Contributor
Contributor
394 Views
Registered: ‎10-29-2018

AXI Traffic Generator IP with high core start pulse

Dear Sir,

I am working on AXI Traffic generator IP. In my design, I am trying to generate random data from IP by giving high core start pulse (core_ext_start), but the design is not working. So, can you please provide some example of this IP which starts generating data after receiving high core_ext_start pulse? I am interested to know about the pulse width of core_ext_start.

Thank you and Regards, Puja Kumari

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11 Replies
Moderator
Moderator
339 Views
Registered: ‎11-09-2015

Re: AXI Traffic Generator IP with high core start pulse

Hi @puja ,

Did you check how it is done in simulation in the example design integrated in vivado?

I would assume that a 1 clk pulse would be enough. Make sure this is a real pulse (low -> high -> low)

Hope that helps,

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Contributor
Contributor
332 Views
Registered: ‎10-29-2018

Re: AXI Traffic Generator IP with high core start pulse

Hi @florentw 

In example design of vivado, external start and stop are not used. Instead, s_axi interface is used.

I simulated design with 10ns clock, reset active for 100ns and start pulse of 10ns. Random data is not being generated. Handshake signal of axi stream interface is not in an active state.

Please help me to debug this issue.

Thank you and Regards,

Puja Kumari

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Moderator
Moderator
328 Views
Registered: ‎11-09-2015

Re: AXI Traffic Generator IP with high core start pulse

Hi @puja ,

Can you share your design?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
322 Views
Registered: ‎10-29-2018

Re: AXI Traffic Generator IP with high core start pulse

Hi @florentw ,

I added AXI Traffic generator IP to my design. Then I wrote following testbench:

module testbench(

);
parameter CLK_PERIOD = 10;
parameter RESET = 100;
parameter start_width = 10;

reg s_axi_aclk;
reg s_axi_aresetn;
reg core_ext_start;
reg core_ext_stop;

wire m_axis_1_tready;
wire [31:0] m_axis_1_tdata;

axi_traffic_gen_0 DUT(
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.core_ext_start(core_ext_start),
.core_ext_stop(core_ext_stop),
.m_axis_1_tready(m_axis_1_tready),
. m_axis_1_tdata( m_axis_1_tdata)
);

initial
begin
s_axi_aclk = 1'b0;
forever #(CLK_PERIOD/2) s_axi_aclk = ~s_axi_aclk;
end

initial
begin
s_axi_aresetn= 1'b0;
#RESET;
s_axi_aresetn = 1'b1;
end

initial
begin
core_ext_start= 1'b0;
#(RESET+3);
core_ext_start = 1'b1;
// # start_width
// core_ext_start= 1'b0;
end

initial
begin
core_ext_stop= 1'b0;


end

endmodule

Thank you and Regards,

Puja Kumari

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Moderator
Moderator
320 Views
Registered: ‎11-09-2015

Re: AXI Traffic Generator IP with high core start pulse

Hi @puja ,

Could you zip you full project and attached it to the topic?

This would help to see how the Traffic generator is added (also I would need the coe file -> I assume you have added them? If not it could be what your issue)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
308 Views
Registered: ‎10-29-2018

Re: AXI Traffic Generator IP with high core start pulse

Hi @florentw ,

PFA

Regards,

Puja Kumari

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Moderator
Moderator
279 Views
Registered: ‎11-09-2015

Re: AXI Traffic Generator IP with high core start pulse

HI @puja ,

One mistake is obvious. You didn't set m_axis_1_tready. If this is not high, the ATG will not send any data.

Also you might need to take care of the interfaces you are not using (S_AXI and S_AXIS). This is never good to leave signals unconnected and undriven.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
269 Views
Registered: ‎10-29-2018

Re: AXI Traffic Generator IP with high core start pulse

Hi @florentw ,

Please find the attached zip file of design.

Now I am using the IP in master loopback mode. I have connected M_AXIS_MASTER interface to S_AXIS_MASTER interface. Still, random data is not being generated. Now, m_axis_1_tready is high, but s_axis_tvalid is always low. I don't the reason behind it. Please help me out to understand this. Please find the attached simulation result.

Also, I do not know how to take care of unconnected interface. Now S_AXI is an unconeected interface in my design. 

Regards,

Puja

 

Capture.PNG
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Moderator
Moderator
265 Views
Registered: ‎11-09-2015

Re: AXI Traffic Generator IP with high core start pulse

HI @puja ,

You need to look into the documentation to konw how to properly connect the AXI interface.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
258 Views
Registered: ‎10-29-2018

Re: AXI Traffic Generator IP with high core start pulse

Hi @florentw ,

I read PG025-AXI Traffic Generator IP Product guide. I could not find what to do with S_AXI interface in case of Master Loopback mode. Also, I am not sure whether unconnected S_AXI interface is the reason for random data not being generated on M_AXIS_MASTER interface.

Please help me to resolve this issue.

Thank you and Regards,

Puja Kumari

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Moderator
Moderator
254 Views
Registered: ‎11-09-2015

Re: AXI Traffic Generator IP with high core start pulse


@puja wrote:

Hi @florentw ,

I read PG025-AXI Traffic Generator IP Product guide. I could not find what to do with S_AXI interface in case of Master Loopback mode. Also, I am not sure whether unconnected S_AXI interface is the reason for random data not being generated on M_AXIS_MASTER interface.

Please help me to resolve this issue.

[Florent] - I already did. You need to connect the AXI interface properly. I am not gonna do all the work for you.

Thank you and Regards,

Puja Kumari


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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