We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Observer p.hayk
Registered: ‎11-21-2013

AXI traffie Generator UG quesitons

Dear Forum,


I am trying to use Xilinx AXI Traffic generator IP, but have several questions from its users guide - ug PG125.

Please help to understand:

1) Can I generate IP only master interface without slave interface? As I understood, there is no option to generate only one interface.

2) Tabel1-2: What is "CMD Memory Format" RAM purpose and what means "Word Offset" section 

3) Fig 1-7, can someone please explain this figure simply. I read the explanation multiple times for Slave-write and read, but still cannot understand how it works.

Tags (1)
0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎10-04-2016

Re: AXI traffie Generator UG quesitons

Hi @p.hayk,

1. There are ways to generate an AXI Traffic Generator (ATG) without the slave interface, but it depends on how you intend to use the ATG on whether this is desirable. The S_AXI interface is how a processor talks to the register interface of the ATG.


2. In Advanced Mode, you use the CMDRAM to describe the exact AXI transactions you want the ATG to send. Each entry in the CMDRAM is 128 bits wide or 4 dwords. The word offset in Table 1-2 indicates to which dword the bits field belongs.


3. Figures 1-7 and 1-8 show how transactions flow through the AXI Traffic Generator when it is in Advanced Mode. 





Don’t forget to reply, kudo, and accept as solution.
0 Kudos