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Observer yetanotherid
Registered: ‎12-08-2014

Best practices for m_axi burst sizes

As I understand it, using memcpy in HLS generates an AXI read or write burst. For communicating with the DDR memory on a Zynq, what are the recommended values for the latency, outstanding, and burst parameters?


I have found that setting the burst too low causes my module to simply hang, i.e. never complete the memory transfer. My first attached screenshot is an example with a max burst of 4 where I almost immediately got an overflow error.


In the second screenshot, the burst length is 16 (the default), and the transfers are working for a while, but then later I get an overflow which I think is due to memory bandwidth limitations.


Why are these transactions hanging forever, and not simply blocking until the handshake is complete? Is it due to the way memcpy gets synthesized?



image formation, burst 4, falling edge of rvalid, did not complete.PNG
image formation, default max burst, falling edge of rvalid, did not complete.PNG
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Xilinx Employee
Xilinx Employee
Registered: ‎10-04-2016

Re: Best practices for m_axi burst sizes

Hi @yetanotherid,

Your default HLS settings are probably okay. The Overflow that you are seeing in your trace reflects the state of the ILA and the number of outstanding transactions it is able to track. A System ILA defaults to tracking 4 transactions (double check in its configuration GUI). If your master can issue more outstanding transactions that the ILA can track, the ILA overflows. This doesn't effect the signal information, it just means the rd/wr_cnt of the ILA is probably wrong.





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