02-11-2019 02:43 AM - edited 02-11-2019 02:47 AM
I'm working on a project that use a Zed Board with Zynq 7Z020 FPGA. I'm making a computer vision back ground subtractor module.
I need to exchange the input image, the output image, 4 big vectors (in/out) and some other parameters (only in).
I'm using axi stream VDMA for the input/output image, the axi lite for the input parameters and the AXI master for the big vectors.
My doubt is the following: Can I use 4 vectors as input output or is better to split and have 4 vectors for the input and 4 vectors for the output?
I'm having communication problems in from the linux program I'm writing. The IP made with Vivado HLS pass the simulation and sinthesis phase.
Below, the vivado structure I have created is following. Any help is welcome. Many thanks in advance
02-11-2019 03:28 AM
I prefer to do everything with a single AXI Master (unless the block is actually talking to multiple AXI Slaves). AXI Masters are pretty big bits of hardware, and adding lots of them can also create a mess of AXI infrastructure - so it's generally nicer to just have a single one on the block that handles all of the input and output.
02-19-2019 08:28 AM
To add on to what @u4223374
There should not be a problem sending multiple vectors through a single AXI Master. Have you confirmed that the hardware works as you expect before moving onto software/Linux? It is really easy to determine if something is a hardware problem if you can simulate and check the hardware before running software on the design.
Once confident in the hardware, then you can be sure it is a software problem which has a seperate debug path. If you haven't tried an example design with VDMA that might be a good place to start as it would give a sanity check. PG020 has a good example design if that would help: https://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v6_2/pg020_axi_vdma.pdf
02-19-2019 08:56 AM
Thanks for your replies,
I havent simulated the design in the way described in pg020_axi_vdma.pdf but the structure is similar to other project. To debug the hardware what I'm doing is to change the IP into something more easyest:
- For the in/out image a simple color converter module form rgb to gray from vivado hls opencv function
02-21-2019 03:34 PM
Have you followed all the Programming Sequence of page 50 in PG020? : https://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v6_2/pg020_axi_vdma.pdf
It seems that if you can confirm you did all those steps, then I would double check that your SW isn't doing anything to change the frames of data which you are not expecting.
02-26-2019 10:43 AM
Thanks Calebd for answer.
I had a look to the sequence recommended by you and It's going better, Now I have a doubt
I have to write te Programming Sequence for every frame I process or only at the beginning?
Now I the result in the attached image.
What I do are the following steps:
- I configure the VDMA with the program sequence and The filter
- I read a frame
- memcopy a in stripe of frame to the ram address where the vdma is going to read
- start the filter
memcopy the out stripe of frame from the ram address and recompose the output image
I don't understand if I'm missing a sync signal.
Many thanks in advance