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Observer smuelhausen
Observer
244 Views
Registered: ‎07-14-2017

Block design AXI external can't be altered

I created an external connection of a HP Axi slave of a Zynq Ultrascale. I changed some the size of the parameters id, aruser and awuser of the port (see appending picture), generated outputs and created HDL wrapper of the block design.

axi.png

But the changes were not inherited. The id parameters had the old size while aruser and awuser were still a std_logic instead of a four bit vector. When I open the configuration of the HP AXI ports, these three parametes are assigned with the comment "auto". So they should be configurable, don't they?

I also tried updating the wrapper file to the desired port definition, only to get a port missmatch during synthesis.

Used Vivado version 2018.2

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Xilinx Employee
Xilinx Employee
204 Views
Registered: ‎10-04-2016

Re: Block design AXI external can't be altered

Hi @smuelhausen ,

Since the ZUS+ PS is a hard block, the width of the USER and ID signals is not configurable. 

Regards,

Deanna

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Observer smuelhausen
Observer
163 Views
Registered: ‎07-14-2017

Re: Block design AXI external can't be altered

Hi Deanna, I also thought about that, but these three parameters of the HP-AXI port are tagged with the label "(Auto)". So I would assume, it is configurable. Best regards
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