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Explorer
Explorer
514 Views
Registered: ‎04-26-2017

DMA - Block Descriptors with several packets

Hello all,

I am working in a system that consist in store data coming from custom IP (8 bytes) to the DMA buffer. To design the DMA I used as a reference the example provided by Xilinx, the polled mode. My problem is that I cannot manage the depth of the DMA. Let me explain it in more detail.

Using this function 'XAxiDma_BdRingCntCalc' I count the number of Block Descriptors I can get in a target region of memory, taking into account the minimum alignemnt between block descriptors. In my case it is set as 0x40, in the variable XAXIDMA_BD_MINIMUM_ALIGNMENT. (If I decrease this alignment, the system doesn't work, so I remain it as it is).

Taking into account the memory region I have, the function determines that I would have 1024 BD. That is ok for me. The problem is when I set how many bytes will my block descriptor has, configured in the MAX_PKT_LEN variable. If I set this MAX_PKT_LEN to 8 bytes, the memory in the DMA is filled as I want BUT, the depth of the DMA is 1024*8 bytes, that is much less than what I want. If I set the MAX_PKT_LEN to 64 bytes (for exemple), only the first 8 bytes of each block descriptor is written, the others until reach 64 bytes are not fulfilled.

My question is, how can I increase the depth of the DMA? Is there a way to change the number of packets included in each Block descriptor?

Any suggestions?

Thanks and best regards,

baldrism

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3 Replies
Xilinx Employee
Xilinx Employee
441 Views
Registered: ‎01-09-2019

Re: DMA - Block Descriptors with several packets

Hello @baldrism,

What direction is your data moving?  Is the data being sent out MM2S?

Can I ask what depth you want in the end?  Or more specifically, how many bytes of data are you trying to send and in how many packets do you want that data sent in?

Edit: To your question about changing the number of packets inside a block descriptor, that is not changeable.  A packet can include a set of BDs, but the end of the BD will trigger the end of the packet.  For setup help regarding the AXI DMA block there is a helpful guide in the AXI DMA Product Guide pages 70 and 71: https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf.

Thanks,

Caleb

Thanks,
Caleb
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Explorer
Explorer
415 Views
Registered: ‎04-26-2017

Re: DMA - Block Descriptors with several packets

Thank you @calebd to reply.

The data is moving from my custom IP (M00_AXIS port) to the dma (S_AXIS_S2MM port). The data is not sent out MM2S. I read this data from the PS in the registers I set to store the RX_BUFFER. The depth I want in the end is 120 Kbytes, I wanted to divide this depth into two blocks of 60Kbytes, that will be filled with the packets I sent from my custom IP. The packets I sent have 8 bytes width. So my intention was to fill the block descriptor with as many 8 bytes packets it can be filled.

I have seen that if I configure M00_AXIS bus of my custom IP in the way that never uses the TLAST signal (it is always '0') this behaviour was achieved. But I don't like this way, because I cannot control when the packet is finished.

If what you say is true and in a buffer descriptor the maxim information that could has is one-packet, how can I increase the number of buffer descriptors up to 15.000 units?

Thanks and best regards,

baldrism

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Xilinx Employee
Xilinx Employee
372 Views
Registered: ‎01-09-2019

Re: DMA - Block Descriptors with several packets

@baldrism,

Here is what I have setup using the example design using Scatter Gather and Interrupts.  The configuration for my AXI DMA looks like this:

baldrism_DMA_setup.PNG

(Edit: Note how the width of the buffer length register was adjusted in order to transfer data at 60 kB/packet.)

With these settings in the example code:

baldrism_DMA_code.PNG

With this configuration I am able to transfer 120 kB between 2 packets, and pass the test provided in the example.  Example code can be found here: https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_intr.c with example design hardware similar to the AR shown here: https://www.xilinx.com/support/answers/58080.html .

 

In your last message you asked about the maximum information that can be sent, and how you could increase the number of buffer descriptors to 15,000.  In the define seen above you can see that the NUMBER_OF_BDS_PER_PKT is set to 1, but that could be greater than 1 if you wanted more buffer descriptors per packet.  There are not more packets in each buffer descriptor.  The value NUMBER_OF_PKTS_TO_TRANSFER should transfer 2 packets with MAX_PKT_LEN size of 60,000 bytes (0xEA60 in hex).  This gives a total of 120 kB transfered between the 2 packets.

Is this a similar setup to what you have configured?

Thanks,

Caleb

Thanks,
Caleb
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