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Observer @ida
Observer
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Registered: ‎03-02-2017

One cycle delay for DMA data to memory transmission over AXI Stream

Hi,

 

I am using the AXI DMA in direct register mode to transfer data from the FPGA to the OCM over the HP ports of the Zynq UltraScale+. For triggering the data transfer i write directly to the address and data length registers and this is working fine. The problem is, that the data only gets written to the memory after I trigger a second transmission on the DMA (so basically with one cycle delay). I can see the data being transmitted over the AXI Stream interface in the hardware debugger but it only gets written to the memory once I trigger a second transmission. Where does the data get stored once it was written over the AXI Stream bus? Can I avoid this delay? I have disabled the cache for the memory region where I am writing to.

 

Thanks!

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Observer @ida
Observer
120 Views
Registered: ‎03-02-2017

Re: One cycle delay for DMA data to memory transmission over AXI Stream

So... I might have an idea why this is happening. I have a custom IP core, which implements a stream interface. This stream interface should link to the DMA, so when the DMA is triggered for data transmission the data is streamed over this interface. Now I noticed that even though I have configured the DMA to send 128 bytes of data after 112 bytes the TVALID signal goes low for one cycle and then high again for the remaining 16 bytes. I am guessing that because of this interrupt the last 4 32-bit data values will be 1 cycle older than the rest. I just don't know why the DMA reacts like this.

Capture_stream.PNG
dma.PNG
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