03-30-2018 11:39 PM
I have created a custom ip with a master and a slave interfaces. I just add the following codes to master and change START_DATA_VALUE and Target Slave Base Addr to 0x0000_0000
reg state; // It isn't used night now initial begin state <= 1'b1; start_single_write <= 1'b1; end
//Write Addresses always @(posedge M_AXI_ACLK) begin if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1) begin axi_awaddr <= 0; end // Signals a new write address/ write data is // available by user logic else if (M_AXI_AWREADY && axi_awvalid) begin //axi_awaddr <= axi_awaddr + 32'h00000004; axi_awaddr <= 32'h00AA_BABA; end end // Write data generation always @(posedge M_AXI_ACLK) begin if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 ) begin axi_wdata <= C_M_START_DATA_VALUE; end // Signals a new write address/ write data is // available by user logic else if (M_AXI_WREADY && axi_wvalid) begin // axi_wdata <= C_M_START_DATA_VALUE + write_index; axi_wdata <= 32'hBABABABA; end end //Read Addresses always @(posedge M_AXI_ACLK) begin if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1) begin axi_araddr <= 0; end // Signals a new write address/ write data is // available by user logic else if (M_AXI_ARREADY && axi_arvalid) begin //axi_araddr <= axi_araddr + 32'h00000004; axi_araddr <= 32'h00AA_BABA; end end always @(posedge M_AXI_ACLK) begin if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1) begin expected_rdata <= C_M_START_DATA_VALUE; end // Signals a new write address/ write data is // available by user logic else if (M_AXI_RVALID && axi_rready) begin expected_rdata <= 32'hBABABABA; end end
I ran simulation and this is the result:
And this is my design:
My question is why WREADY is not asserted?
OS: Xubuntu 16.04
04-04-2018 10:46 AM
Your master is violating AXI Protocol by asserting AWVALID but not presenting a valid AWADDR until two clocks later. There is a similar problem on the write data interface where WVALID is asserted but the WDATA is not presented until four clocks later.
This is causing the Interconnect to latch the AWADDR = 32'hXXXXXXXX and WDATA = 32'hXXXXXXXX.
For further details on AXI Protocol, please refer to the ARM AXI Protocol Specification (IHI 0022E). You will have to register with ARM to download the document.
04-04-2018 03:05 PM
04-04-2018 03:46 PM
I recommend starting with the AXI templates that are included with IP Packager rather than trying to write your AXI interface from scratch. The templates handle the protocol details and provide comments to help you integrate your custom code with the AXI interface.
Chapter 3 of UG1118 walks through the steps to create a new AXI4 peripheral.
04-12-2018 11:29 AM
@demarcoThank you for answer. I have read document that you recommend but i can't able to find out what i am doing wrong. So i have create an other ip and i sticked to pre-written templates with small changes. You can find codes in the attachment.
This is the screenshots:
I would really appreciate if you could help me.
04-13-2018 01:07 PM
I believe your ILA trace is showing either the M_AXI_GP0 interface between the Zynq and the Interconnect or the M00_AXI interface between the Interconnect and myIP.
It looks like the write address and write data channels for myIP are behaving correctly for the write to address 0x4000_0000. The write response channel, however, doesn't appear to be sending anything. I would expect myIP to finish the write transaction by asserting BVALID and driving the appropriate response on BRESP back to the Zynq.
Please take a look at the BRESP code in myIP and see if you can figure out why it isn't responding.
04-16-2018 01:36 AM - edited 04-16-2018 10:53 AM
Thank you very much for your answer. I have change PS' slave port from HP to GP and write transaction worked. However, read transaction still does not operate. I believe that problem is rvalid does not asserted by master. I don't know how to make it right. I trace it until GP port. After that, i don't know what happens. I haven't change a thing in original template but some parameters. I don't know it changes a thing, i'm using Vivado 2017.1. Here is the screen shoots to see clear.
Thank you very much for your effort.
I have tried to validate the ip by following this wiki page. And it worked.
So i believe that ip is correct, something wrong with ps or interconnect.
04-16-2018 03:39 PM
It still looks like there are some AXI protocol issues in this design.
Instead of the AXI verification IP I would add the AXI Protocol Checker IP and have it connected to the AXI buses that go between the PS and the AXI Interconnected and the AXI Interconnect to myIP.
04-16-2018 04:21 PM
04-16-2018 04:31 PM
You need to make sure the output ports of the AXI protocol checkers are logged in your simulations. When looking for errors you first need to see if pc_asserted gets set to '1' which indicates an error occurred and then you need to look at the pc_status bits to decode the detected error. PG101 has the information on how to decode the pc_status signals. Here's a link to the latest version:
04-16-2018 11:30 PM
Hello @ryana ,
I took a look at pc_asserted bu it never set to 1. I don't know it is change a thing but following message appears when i run simulation.
XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.M_AXI_GP0.master  : *ZYNQ_BFM_INFO : M_AXI_GP0 : Port is ENABLED. XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.M_AXI_GP1.master  : *ZYNQ_BFM_INFO : M_AXI_GP1 : Port is DISABLED. XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.S_AXI_GP0.slave  : *ZYNQ_BFM_INFO : S_AXI_GP0 : Port is ENABLED. XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.S_AXI_GP1.slave  : *ZYNQ_BFM_INFO : S_AXI_GP1 : Port is DISABLED. XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.S_AXI_HP0.slave  : *ZYNQ_BFM_INFO : S_AXI_HP0 : Port is DISABLED. XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.S_AXI_HP1.slave  : *ZYNQ_BFM_INFO : S_AXI_HP1 : Port is DISABLED. XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.S_AXI_HP2.slave  : *ZYNQ_BFM_INFO : S_AXI_HP2 : Port is DISABLED. XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.S_AXI_HP3.slave  : *ZYNQ_BFM_INFO : S_AXI_HP3 : Port is DISABLED. XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.S_AXI_ACP.slave  : *ZYNQ_BFM_INFO : S_AXI_ACP : Port is DISABLED.
Thank you very much
04-17-2018 10:36 AM - edited 04-17-2018 10:42 AM
The messages you are receiving from the VIP are expected.
Are you able to upgrade Vivado to 2018.1? We had some issues in the Zynq 7000 VIP where the slave ports didn't always respond to read transactions. There were a few fixes in 2018.1 to address these bugs. I'm wondering if you are running into a known issue.
Another thing that can keep the slave ports from working correctly is not resetting the PS VIP. Your reset code should look something like this:
//Reset the PL
tb_ARESETn = 1'b0;
tb_ARESETn = 1'b1;
repeat(5) @(posedge tb_ACLK);
04-17-2018 10:46 AM - edited 04-17-2018 10:47 AM
04-17-2018 11:16 AM
Can you re-post your warnings? They are too small to read in your previous post.
04-18-2018 09:08 AM
Those Critical Warnings would impact behavior of the hardware, but not in simulation. That is a separate issue and needs a separate thread.
Could you explain what you mean when you say you haven't written a test bench? How can you just use the wrapper for simulation? How are you applying clocks and reset to the system?
If you need a skeleton Zynq-7000 test bench to start from, there is one built into Vivado. You can access it from Vivado via the File->Open Example Design... menu and choosing Base Zynq
04-18-2018 11:21 AM
I took your advice and create a test bench. It is like this:
module test_bench(); reg tb_ACLK; reg tb_ARESETn; wire temp_clk; wire temp_rstn; initial begin tb_ACLK = 1'b0; end always #10 tb_ACLK = !tb_ACLK; initial begin tb_ARESETn = 1'b0; repeat(20)@(posedge tb_ACLK); tb_ARESETn = 1'b1; @(posedge tb_ACLK); repeat(5) @(posedge tb_ACLK); //Reset the PL test_bench.init.design_1_i.processing_system7_0.inst.fpga_soft_reset(32'h1); test_bench.init.design_1_i.processing_system7_0.inst.fpga_soft_reset(32'h0); end assign temp_clk = tb_ACLK; assign temp_rstn = tb_ARESETn; design_1_wrapper init ( .DDR_addr(), .DDR_ba(), .DDR_cas_n(), .DDR_ck_n(), .DDR_ck_p(), .DDR_cke(), .DDR_cs_n(), .DDR_dm(), .DDR_dq(), .DDR_dqs_n(), .DDR_dqs_p(), .DDR_odt(), .DDR_ras_n(), .DDR_reset_n(), .DDR_we_n(), .FIXED_IO_ddr_vrn(), .FIXED_IO_ddr_vrp(), .FIXED_IO_mio(), .FIXED_IO_ps_clk(temp_clk), .FIXED_IO_ps_porb(temp_rstn ), .FIXED_IO_ps_srstb(temp_rstn) ); endmodule
However, it does not change a thing. Is there any configuration that i should do to PS in order to execute read transaction?
04-25-2018 09:53 AM
Does your IP require a few register writes to set it up before it begins to send read transactions to the PS?
Or do you need to add a delay at the end of your test bench to give your master time to start sending reads to the PS?
04-25-2018 12:04 PM
For now, it does not require any register, In the future, I'll use 2 registers to calculate read address' and 1 register for initiate transaction. But it's just a plan for SDK.
Couple days ago, I have try to connect it to BRAM through interconnect and AXI BRAM Controller, it worked in simulation but not in SDK.
-Thank you very much