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Contributor
Contributor
1,075 Views
Registered: ‎07-04-2017

Write transaction does not work

Hello everyone,

 

I have created a custom ip with a master and a slave interfaces. I just add the following codes to master and change START_DATA_VALUE and Target Slave Base Addr to 0x0000_0000 

 

reg state; // It isn't used night now
initial begin
state <= 1'b1;
start_single_write <= 1'b1;
end
  //Write Addresses
	  always @(posedge M_AXI_ACLK)
	      begin
	        if (M_AXI_ARESETN == 0  || init_txn_pulse == 1'b1)
	          begin
	            axi_awaddr <= 0;
	          end
	          // Signals a new write address/ write data is
	          // available by user logic
	        else if (M_AXI_AWREADY && axi_awvalid)
	          begin
	            //axi_awaddr <= axi_awaddr + 32'h00000004;
	             axi_awaddr <= 32'h00AA_BABA;
	          end
	      end

	  // Write data generation
	  always @(posedge M_AXI_ACLK)
	      begin
	        if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
	          begin
	            axi_wdata <= C_M_START_DATA_VALUE;
	          end
	        // Signals a new write address/ write data is
	        // available by user logic
	        else if (M_AXI_WREADY && axi_wvalid)
	          begin
	           // axi_wdata <= C_M_START_DATA_VALUE + write_index;
	           axi_wdata <= 32'hBABABABA;
	          end
	        end

	  //Read Addresses
	  always @(posedge M_AXI_ACLK)
	      begin
	        if (M_AXI_ARESETN == 0  || init_txn_pulse == 1'b1)
	          begin
	            axi_araddr <= 0;
	          end
	          // Signals a new write address/ write data is
	          // available by user logic
	        else if (M_AXI_ARREADY && axi_arvalid)
	          begin
	            //axi_araddr <= axi_araddr + 32'h00000004;
							axi_araddr <= 32'h00AA_BABA;


	          end
	      end



	  always @(posedge M_AXI_ACLK)
	      begin
	        if (M_AXI_ARESETN == 0  || init_txn_pulse == 1'b1)
	          begin
	            expected_rdata <= C_M_START_DATA_VALUE;
	          end
	          // Signals a new write address/ write data is
	          // available by user logic
	        else if (M_AXI_RVALID && axi_rready)
	          begin
	            expected_rdata <= 32'hBABABABA;
	          end
	      end

 

I ran simulation and this is the result:

vivado_sim.png

 

And this is my design:

design.png

 

My question is why WREADY is not asserted?

 

 

Device: Zybo

OS: Xubuntu 16.04

 

Thank you

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18 Replies
Xilinx Employee
Xilinx Employee
996 Views
Registered: ‎10-04-2016

Re: Write transaction does not work

Hi @ercumentkaya,

Your master is violating AXI Protocol by asserting AWVALID but not presenting a valid AWADDR until two clocks later. There is a similar problem on the write data interface where WVALID is asserted but the WDATA is not presented until four clocks later.

 

This is causing the Interconnect to latch the AWADDR = 32'hXXXXXXXX and WDATA = 32'hXXXXXXXX.

 

For further details on AXI Protocol, please refer to the ARM AXI Protocol Specification (IHI 0022E). You will have to register with ARM to download the document.

 

https://silver.arm.com/download/download.tm?pv=1377613

 

Regards,

 

Deanna

 

 

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Contributor
Contributor
982 Views
Registered: ‎07-04-2017

Re: Write transaction does not work

@demarco Thank you for your answer. I'm little confused about what to do. Could you tell proper examples for write and read transactions if it is possible.

 

Regards.

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Xilinx Employee
Xilinx Employee
977 Views
Registered: ‎10-04-2016

Re: Write transaction does not work

Hi @ercumentkaya,

I recommend starting with the AXI templates that are included with IP Packager rather than trying to write your AXI interface from scratch. The templates handle the protocol details and provide comments to help you integrate your custom code with the AXI interface.

 

Chapter 3 of UG1118 walks through the steps to create a new AXI4 peripheral.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1118-vivado-creating-packaging-custom-ip.pdf#page=26

 

Regards,

 

Deanna

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Contributor
Contributor
897 Views
Registered: ‎07-04-2017

Re: Write transaction does not work

@demarcoThank you for answer. I have read document that you recommend but i can't able to find out what i am doing wrong. So i have create an other ip and i sticked to pre-written templates with small changes. You can find codes in the attachment. 

 

This is the screenshots:

 

Screenshot_2018-04-12_21-04-02.png

Screenshot_2018-04-12_21-03-33.png

 

I would really appreciate if you could help me.

 

-Thank you

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Xilinx Employee
Xilinx Employee
879 Views
Registered: ‎10-04-2016

Re: Write transaction does not work

Hi @ercumentkaya,

I believe your ILA trace is showing either the M_AXI_GP0 interface between the Zynq and the Interconnect or the M00_AXI interface between the Interconnect and myIP. 

 

It looks like the write address and write data channels for myIP are behaving correctly for the write to address 0x4000_0000. The write response channel, however, doesn't appear to be sending anything. I would expect myIP to finish the write transaction by asserting BVALID and driving the appropriate response on BRESP back to the Zynq.

 

Please take a look at the BRESP code in myIP and see if you can figure out why it isn't responding. 

 

Regards,

 

Deanna

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Contributor
Contributor
863 Views
Registered: ‎07-04-2017

Re: Write transaction does not work

Hi @demarco,

 

Thank you very much for your answer. I have change PS' slave port from HP to GP and write transaction worked. However, read transaction still does not operate. I believe that problem is rvalid does not asserted by master. I don't know how to make it right. I trace it until GP port. After that, i don't know what happens. I haven't change a thing in original template but some parameters. I don't know it changes a thing, i'm using Vivado 2017.1. Here is the screen shoots to see clear.

 

write_works.png

 

read_does_not.png

 

Interconnect_slave.png

 

Interconnect_master.png

 

PS_Slave.png

 

Thank you very much for your effort.

 

Update:

I have tried to validate the ip by following this wiki page. And it worked. 

 

design.png

 

vip.png

 

So i believe that ip is correct, something wrong with ps or interconnect.

 

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Moderator
Moderator
821 Views
Registered: ‎11-28-2016

Re: Write transaction does not work

Hello @ercumentkaya,

 

It still looks like there are some AXI protocol issues in this design.

Instead of the AXI verification IP I would add the AXI Protocol Checker IP and have it connected to the AXI buses that go between the PS and the AXI Interconnected and the AXI Interconnect to myIP.

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Contributor
Contributor
815 Views
Registered: ‎07-04-2017

Re: Write transaction does not work

Hello @ryana

 

I have add ip checkers, as follows and the results are below. I haven't use ip checkers so i don't know values correct or not.

design_with_ipchecker.png

ip_checker.png

ip_checker2.png

ip_checker3.png

 

Screenshots are in order. 

 

-Thank you very much

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Moderator
Moderator
808 Views
Registered: ‎11-28-2016

Re: Write transaction does not work

Hello @ercumentkaya,

 

You need to make sure the output ports of the AXI protocol checkers are logged in your simulations.  When looking for errors you first need to see if pc_asserted gets set to '1' which indicates an error occurred and then you need to look at the pc_status bits to decode the detected error. PG101 has the information on how to decode the pc_status signals.  Here's a link to the latest version:

https://www.xilinx.com/support/documentation/ip_documentation/axi_protocol_checker/v2_0/pg101-axi-protocol-checker.pdf

 

 

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Contributor
Contributor
808 Views
Registered: ‎07-04-2017

Re: Write transaction does not work

Hello @ryana ,

 

I took a look at pc_asserted bu it never set to 1. I don't know it is change a thing but following message appears when i run simulation.

XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.M_AXI_GP0.master
[0] : *ZYNQ_BFM_INFO : M_AXI_GP0 : Port is ENABLED.
XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.M_AXI_GP1.master
[0] : *ZYNQ_BFM_INFO : M_AXI_GP1 : Port is DISABLED.
XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.S_AXI_GP0.slave
[0] : *ZYNQ_BFM_INFO : S_AXI_GP0 : Port is ENABLED.
XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.S_AXI_GP1.slave
[0] : *ZYNQ_BFM_INFO : S_AXI_GP1 : Port is DISABLED.
XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.S_AXI_HP0.slave
[0] : *ZYNQ_BFM_INFO : S_AXI_HP0 : Port is DISABLED.
XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.S_AXI_HP1.slave
[0] : *ZYNQ_BFM_INFO : S_AXI_HP1 : Port is DISABLED.
XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.S_AXI_HP2.slave
[0] : *ZYNQ_BFM_INFO : S_AXI_HP2 : Port is DISABLED.
XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.S_AXI_HP3.slave
[0] : *ZYNQ_BFM_INFO : S_AXI_HP3 : Port is DISABLED.
XilinxAXIVIP: Found at Path: design_1_wrapper.design_1_i.processing_system7_0.inst.S_AXI_ACP.slave
[0] : *ZYNQ_BFM_INFO : S_AXI_ACP : Port is DISABLED.

Thank you very much

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Xilinx Employee
Xilinx Employee
793 Views
Registered: ‎10-04-2016

Re: Write transaction does not work

Hi @ercumentkaya,

The messages you are receiving from the VIP are expected.

 

Are you able to upgrade Vivado to 2018.1? We had some issues in the Zynq 7000 VIP where the slave ports didn't always respond to read transactions. There were a few fixes in 2018.1 to address these bugs. I'm wondering if you are running into a known issue.

 

Another thing that can keep the slave ports from working correctly is not resetting the PS VIP. Your reset code should look something like this:

 

//Reset the PL
tb.zynq_sys.base_zynq_i.processing_system7_0.inst.fpga_soft_reset(32'h1);
tb_ARESETn = 1'b0;
repeat(20)@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);

repeat(5) @(posedge tb_ACLK);

tb.zynq_sys.base_zynq_i.processing_system7_0.inst.fpga_soft_reset(32'h0);

 

Regards,

 

Deanna

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Contributor
Contributor
782 Views
Registered: ‎07-04-2017

Re: Write transaction does not work

Hi @demarco,

 

I have upgraded today. I had same result but i had following critical warnings. 

 

Screenshot_2018-04-17_17-57-03.png

 

I haven't wrote a test bench and i'm using wrapper for simulation.

 

-Thank you

 

 

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Xilinx Employee
Xilinx Employee
772 Views
Registered: ‎10-04-2016

Re: Write transaction does not work

Hi @ercumentkaya,

Can you re-post your warnings? They are too small to read in your previous post.

 

Regards, 

 

Deanna

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Contributor
Contributor
762 Views
Registered: ‎07-04-2017

Re: Write transaction does not work

Hi @demarco

 

Here is it.

 

Screenshot_2018-04-17_17-57-03.png

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Xilinx Employee
Xilinx Employee
739 Views
Registered: ‎10-04-2016

Re: Write transaction does not work

Hi @ercumentkaya,

Those Critical Warnings would impact behavior of the hardware, but not in simulation. That is a separate issue and needs a separate thread.

 

Could you explain what you mean when you say you haven't written a test bench? How can you just use the wrapper for simulation? How are you applying clocks and reset to the system?

 

If you need a skeleton Zynq-7000 test bench to start from, there is one built into Vivado. You can access it from Vivado via the File->Open Example Design... menu and choosing Base Zynq

 

Regards,

 

Deanna

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Contributor
Contributor
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Registered: ‎07-04-2017

Re: Write transaction does not work

Hi @demarco

 

I took your advice and create a test bench. It is like this:

 

module test_bench();
    
    reg tb_ACLK;
    reg tb_ARESETn;
   
    wire temp_clk;
    wire temp_rstn; 
   
    initial 
      begin       
          tb_ACLK = 1'b0;
      end
      
    always #10 tb_ACLK = !tb_ACLK;
     
    initial begin
        
         tb_ARESETn = 1'b0;
         repeat(20)@(posedge tb_ACLK);        
         tb_ARESETn = 1'b1;
         @(posedge tb_ACLK);
         
         repeat(5) @(posedge tb_ACLK);
           
         //Reset the PL
         test_bench.init.design_1_i.processing_system7_0.inst.fpga_soft_reset(32'h1);
         test_bench.init.design_1_i.processing_system7_0.inst.fpga_soft_reset(32'h0);
     end
     assign temp_clk = tb_ACLK;
     assign temp_rstn = tb_ARESETn;
            
design_1_wrapper init (
    .DDR_addr(),
    .DDR_ba(),
    .DDR_cas_n(),
    .DDR_ck_n(),
    .DDR_ck_p(),
    .DDR_cke(),
    .DDR_cs_n(),
    .DDR_dm(),
    .DDR_dq(),
    .DDR_dqs_n(),
    .DDR_dqs_p(),
    .DDR_odt(),
    .DDR_ras_n(),
    .DDR_reset_n(),
    .DDR_we_n(),
    .FIXED_IO_ddr_vrn(),
    .FIXED_IO_ddr_vrp(),
    .FIXED_IO_mio(),
    .FIXED_IO_ps_clk(temp_clk),
    .FIXED_IO_ps_porb(temp_rstn ),
    .FIXED_IO_ps_srstb(temp_rstn)
    );
    
endmodule

However, it does not change a thing. Is there any configuration that i should do to PS in order to execute read transaction?

 

Thank you

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Xilinx Employee
Xilinx Employee
698 Views
Registered: ‎10-04-2016

Re: Write transaction does not work

Hi @ercumentkaya,

Does your IP require a few register writes to set it up before it begins to send read transactions to the PS?

 

Or do you need to add a delay at the end of your test bench to give your master time to start sending reads to the PS?

 

Regards,

 

Deanna

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Contributor
Contributor
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Registered: ‎07-04-2017

Re: Write transaction does not work

Hi @demarco,

 

For now, it does not require any register, In the future, I'll use 2 registers to calculate read address' and 1 register for initiate transaction. But it's just a plan for SDK.

 

Couple days ago, I have try to connect it to BRAM through interconnect and AXI BRAM Controller, it worked in simulation but not in SDK.

 

-Thank you very much

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