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Observer li_zicong
Registered: ‎04-28-2017

axi bus bandwidth

I had read a paper "Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks ". I don't understand the word in red. why the number of the axi ip , the more the bandwidth will be. 

In my limited knowledge, I think if one axi ip start using the bus, the other IP will wait until the axi ip end. 

Page 168  4.4 The purposes of using external data transfer engines are in two folds: 1) It can provide data transfer between accelerator and external memory; 2) It can isolate our accelerator from various platform and tool specific bandwidth features.
Figure 13 shows an experiment with AXI4 bus bandwidth in Vivado 2013.4. In these two figures, we set two parameters,
bitwidth of AXI bus to DRAM controller and DRAM controller’s external bandwidth, at their highest configurations
while changing the number of IP-AXI interfaces and the bitwidth of each IP. In Figure 13(a), the increase in IP-AXI interface bitwidth has no effect on bandwidth (400MB/s under 100MHz frequency). In Figure 13(b), with more IP interfaces added to AXI bus, its bandwidth increases almost linearly and the highest bandwidth is about 4.5 GB/s. In our CNN accelerator design, a minimal bandwidth of 1.55 GB/s is required. Therefore, 4 IP interfaces are sufficient for this design according to Figure 13. We use two AXI-IP interfaces in data transfer engine 0 and two in data transfer engine 1, as is shown in Figure 10.

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Scholar hbucher
Registered: ‎03-22-2016

Re: axi bus bandwidth

@li_zicong Probably the reads/ writes  are not exploiting the burst capacity of the DDR.

Aren't you one of the authors?

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Observer li_zicong
Registered: ‎04-28-2017

Re: axi bus bandwidth

I am not one of authors. I just read the paper from IEEE

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