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Visitor brinda_wh
Visitor
220 Views
Registered: ‎12-05-2018

problem with AXI data stream

hi

I've designed a 16bit Data Counter with a ready flag in PL.each time a number is added to the  Counter, the flag is one time low to  high.The speed of the counter is 1Mbp/s.Now I want send these data to PS.

 At first i used AXI-LITE custom IP,I defined 512 registers, each flag change, a registry is filled with Counter data.Finally, after the 512 registry is filled, there is an external interruption to the arm,and ARM  start reading the memory with the following command

Xuint32* baseaddr_p = (Xuint32*)   MYIP_BASEADDR;

for(i=0;i<512;i++){
read_data[i]=*(baseaddr_p+i);
}

But after receiving several 512  packets, the data is invalid

To solve this problem i want use AXI-STREAM FIFO and DMA

Now I have some questions

How i send Counter data into AXI-STREAM FIFO?

is There  any example or study in this case?

 

 

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1 Reply
Voyager
Voyager
152 Views
Registered: ‎02-01-2013

Re: problem with AXI data stream

 

The AMBA AXI Stream specification is available online. You might want to secure a copy for reference.

You can fashion an AXI Stream Master interface pretty easily. The Counter value becomes TDATA; your flag becomes TVALID. There will be a TREADY signal from the AXI Stream FIFO, but you can ignore it if you want to keep things simple. You should monitor if TREADY is ever low when TVALID is high, and create an interrupt or exception at that time--since you just lost some data. But if the DMA device is working, that shouldn't happen at the data rates you're talking about.

-Joe G.

 

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