cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Only evaluation kit with the full gamut of 56G interfaces, available now

tech-blogs
Xilinx Employee
Xilinx Employee
2 10 3,129

Xilinx has introduced the Virtex® UltraScale+™ 56G PAM4 VCU129 FPGA evaluation kit to enable the design of a next-generation networking platform, bringing unparalleled adaptability and performance.

Virtex UltraScale+ 58G PAM4 FPGAs are built upon the same building blocks used by the Xilinx 16nm UltraScale+ FPGA family and have integrated PAM4 transceiver, KP4 FEC, 100GE, and 150G interlaken blocks.

The PAM4 transceivers in these Virtex UltraScale+ FPGAs are another great example of Xilinx’s transceiver technology leadership. With a variety of 56G interfaces on the VCU129 evaluation kit, designers can evaluate upcoming optics, cables, and protocols to build a future-proofing platform while preserving their existing investment.

VCU129 evaluation kit provides

  • Common high-speed interconnects for real-world evaluation
  • Onboard peripherals and memories for broad applications
  • Superior SerDes technology and thermal management

This VCU129 evaluation kit has everything you need to prototype your applications using Virtex UltraScale+ 58G PAM4 FPGAs.

vcu129_board_edm.png

For more information:

10 Comments
marcelo.guedes

Wonderful product, but I noticed that this board doesn't have a FMC+ interface for expansion boards. What do you guys suggest to add basic GPIOs in a project over VCU129 for general controllers, status and data interfaces in a large project? How many user-configurable on-board GPIOs exists on VCU129?

tech-blogs
Xilinx Employee
Xilinx Employee

Hi @marcelo.guedes,

Thank you for the comment. The only GPIOs that are user accessible on the VCU129 go to the User I/Os & LEDs. With that said, one other I/O expansion option might be the PCIe interface. User can use the following cable and host adapter card for additional interfaces.

marcelo.guedes

Great! Thank you for the answer.

Another question: any idea when will we have access to the board manual on Xilinx page? Right now the "Documentation" section is empty:

https://www.xilinx.com/products/boards-and-kits/vcu129-pp.html#documentation

tech-blogs
Xilinx Employee
Xilinx Employee

Hi @marcelo.guedes, the related documents will be available within few days on xilinx.com.

 

vpalli_aquantia

Hi, 

i am looking for the schematic for this board but could not locate on the eval kit web page. Any leads on it?

As of now i am curious if there are bidirectional level shifters (1.8V <-> 3.3V) present for the PMOD interface of the board. I am planning to use the PMOD connector to interface with another controller that runs at 3.3V IO. 

in the kit's user guide , i have seen references to level shifters for I2C interfaces but not this connector. Another eval kit VCU118 has level shifter for the PMOD inteface as well. I am hopeful that this board has it too but probably not mentioned in the user guide , hence looking for the schematic. 

Kindly help. 

 

Thanks,

Venkat

 

tech-blogs
Xilinx Employee
Xilinx Employee

Please reach out to your local sales rep or our forum for technical support https://forums.xilinx.com/

tansua
Observer
Observer
tech-blogs
Xilinx Employee
Xilinx Employee

@tansua, VCU129 is using full production Virtex UltraScale+ XCVU29P FPGA while VCU129-PP features pre-production Virtex UltraScale+ XCVU29P FPGA.Vll Virtex UltraScale+ 58G PAM4 FPGAs in full production.

ensilica_davidw

I can't see a way of enabling Interlaken or PCIe to use 58G PAM4 on the SERDES.  These protocols only seem to support NRZ on GTMs. The only option for GTM PAM4 seems to be Ethernet GAU-2.

interlaken.png

xtech-blogs
Xilinx Employee
Xilinx Employee

@ensilica_davidw 

For Virtex UltraScale+ 58G PAM4 FPGAs, the wizard does not generate the entire IP for a particular interface, just the PHY. What the template drop down does is auto-fill selections in the rest of the wizard, so making the correct rate/loss selections in the wizard will enable identical support. For PCIe support, the Ultrascale+ GTY transceiver supports PCIe up to Gen4 including line rate, CDR bandwidth requirements and some other PHY specific requirements. For more information for PCIe, please visit https://www.xilinx.com/products/technology/pci-express.html#uspluspcie.