Editor’s Note: This content is contributed by Doug Zielinski, Senior FPGA Design and Support Engineer, DesignLinx Solutions, Inc.
The Xilinx® Vivado® Design Suite’s IP integrator provides an excellent way to build custom designs using Xilinx IP or custom IP using block designs. Users can place these block designs into a hierarchical block, which can then be part of an overall hierarchical design. This is a great way to build complex hierarchical designs in a project.
But what if you’d like to use one of these great block designs that you’ve created in a different Vivado project? These block designs cannot simply be copied into another project and used in a block design within that project.
I recently learned of a simple method to use a block design from one project in a block design of a separate Vivado project.
The Write Block Design Tcl Command
Vivado provides a command that will write a Tcl script to recreate the block design. After the user creates a block design, the user uses the write_bd_tcl command to create the Tcl script. The user then runs this script in a separate Vivado project to create the block design in that project.
The block design is simply a separate block design in the project. The user can open, copy, and paste the newly added block design into an existing block design within the project.
A Simple Example
I created a couple of simple Vivado 2019.2.1 projects to show how one block design can simply be copied into a different Vivado project. I also created a simple custom IP block, which is part of the block design to be copied. Here is a block design of project_1. It contains a fir compiler block as well as an axis switch with 2 slave ports and 1 master port.
Let’s say I want to connect a block design from another project to the spare S01_AXIS port.
Here is a list of sources for the project. Only the filter_1 block design is shown.
The following picture shows the block design of the second project, project_2.
This project contains an AXIS streaming FIFO, a piece of custom IP called data_manip_0, and a fir compiler. I want to get this block design into project_1. Here are the instructions.
Put the block design into a hierarchical block by selecting the IP contained in the block design: right click and select create hierarchy option. The hierarchy block now looks like this:
Next, enter the write_bd_tcl command in the Tcl console with the block design opened.
Now, create the block design and generate a block design Tcl script for project_2. Add the repository for the custom IP block, data_manip_0 to project_1. Open the IP catalog in project_1 and right click in the window. Click Add Repository and select the path where the IP resided.
The following picture shows the repository is now added to the IP catalog.
Execute the block design Tcl command in project_1 to bring in the block design from project_2.
The source window now shows the filter_2 block design has been added to project_1.
Select the sub1_hier block shown above, then copy, and paste into the filter_1 block design. The new block design is shown below:
The sub1_hier is expanded, and there is a full block design, including the custom data_manip_0 IP block.
The user can validate and generate the block design at this point, and remove the filter_2 block design the project as well.
As you can see from the example above, Vivado users can copy custom block designs from one Vivado project to another by using the powerful write_bd_tcl command. Another benefit is that users can reuse the proven block design across multiple Vivado projects.
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