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Partner: Creating Allegro Hdl, Altium, Mentor, Orcad or Zuken schematic symbols for the humongous Virtex Ultrascale+ VU19P FPGAs

xtech-blogs
Xilinx Employee
Xilinx Employee
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Editor’s Note: This content is contributed by Bill OLeary at CadEnhance

 

The Xilinx® Virtex® UltraScale+™ VU19P FPGA provides the highest logic density and I/O count on a single device ever built in 16nm FPGA, enabling emulation and prototyping, as well as test, measurement, compute, networking, aerospace, and defense-related applications. Your company just decided to use it in your next product. That’s great news for your company and your future. This giant will muscle in on some new market share and provide flexible upgrade paths for the next five years!

While the VU19P is supported by an extensive set of debug, visibility tools, and IP, the sheer size of this part creates a pain point for the librarians or hardware designers who need to create functional symbols to represent every pin in the device in their schematics.

How can you get this behemoth into your design quickly and with no fear of errors?

PartBuilder from CadEnhance provides the answer. With partBuilder you can create 66 symbols for the VU19P devices in under 15 minutes.

Suppose you need to customize the set of symbols to meet your needs or standards better. In that case, you can create the exact set you want in less than an hour by modifying the Symbol Description Language (SDL) that PartBuilder created to draw the initial set of symbols.

This SDL REPLICATE LOOP creates 23 Symbols, one for each bank pair in the loopThis SDL REPLICATE LOOP creates 23 Symbols, one for each bank pair in the loop

 

This is one of the bank pairs (HP I/O banks 29 and 69) created by the loopThis is one of the bank pairs (HP I/O banks 29 and 69) created by the loop

PartBuilder extracts the pin data from the native package  file generated by the Vivado® Design Suite. This ensures accurate import of every device pin, including important parameters like pin-delay so you can sleep at night. Once you’ve created a symbol for a Xilinx device family, Partbuilder’s reuse makes it that much easier to create symbols for another device in the same family. 

While you are at it, our good friend over at dalTools created this video showing how to create the PCB footprint for Allegro in about 5 minutes. If you want to see the detailed process, check out this video playlist.

 

PartBuilder from CadEnhance automates the creation of FPGA symbols for devices with 50 to 5000+ Pins. Symbols for any size device can be easily created in less than an hour.

PartBuilder uses built-in FPGA intelligence to quickly and accurately divide these parts into interchangeable functional symbol blocks making it easy to work within the schematic. The Symbol Description Language (SDL) enables easy manipulation to create the final symbol set you need, instead of forcing you to use one generic solution.  

Just as important, the symbols are built using your exacting library standards with fully programmable property content and locations. Thanks to the automation, PartBuilder can extract and add important additional pin-attributes, including pin-delay and diff-pair identification, that most symbol libraries lack today due to the task's daunting nature.

 

Sign up for a demo with one of our experts today, and you’ll get access to the symbols we created in the demo video. You’ll be able to use our complete tool free for 1 month to customize the symbols to your needs. When you download the tool, you also get the FREE AllegroHDL, Orcad, and Mentor symbol viewer providing easy access to part and pin properties and powerful pin name and pin number searches across symbols not seen in the standard EDA vendor toolsets.