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Partner: Designing Wireless Systems with Xilinx Zynq UltraScale+ RFSoC and MATLAB and Simulink

Xilinx Employee
Xilinx Employee
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Editor’s Note: This content is contributed by Noam Levine, Partner Manager at Mathworks


Traditionally, the RF design world and digital design worlds were separated. That has changed now that the Xilinx® Zynq® UltraScale+™ RFSoC has brought them together in one device. The Zynq® UltraScale+™ RFSoC revolutionized RF and wireless systems by introducing a programmable device with integrated RF data converters. MATLAB® and Simulink® help engineers work across both RF and digital domains, get the most out of their RF hardware, and save time and effort in developing and deploying their wireless processing algorithms on highly integrated devices like the Zynq UltraScale+ RFSoC.


It Starts with RF System Characterization

Characterizing RF throughput performance is a critical first step in wireless system design. Avnet’s RFSoC Explorer (fig. 1) provides a MATLAB-based characterization framework, leveraging LTE and 5G standards-compliant and custom waveforms, along with appropriate measurement tools and visualizations.

Figure 1 - RFSoC Explorer from Avnet connects MATLAB to RFSoC hardware to measure RF performanceFigure 1 - RFSoC Explorer from Avnet connects MATLAB to RFSoC hardware to measure RF performance


Optimizing Algorithm Performance through Simulation

Once RF performance has been characterized, wireless algorithms can be validated and deployed on hardware to take the best advantage of RFSoC performance.

MATLAB and Simulink provide a design language that RF and communications engineers use to develop and validate signal processing algorithms and share them across different workgroups in their organizations. With the giga-sample-per-second data-converter integration on RFSoC, RF engineers may be exploring hardware deployment for the first time. They may not be familiar with SoC programming environments. These engineers just need a path to get their ideas running on hardware. More experienced programmers, looking to enhance execution performance, will want to explore partitioning algorithm tasks between the Zynq UltraScale+ RFSoC’s programmable logic and processing system and determine elements like FIFO sizes and memory bandwidth.

For both novice and experienced programmers, a system-architecture-simulation tool like SoC Blockset™ (fig 2) is an essential first step both for getting algorithms running in hardware and for then helping engineers benchmark execution and decide how to best use the resources on RFSoC to ensure optimal data flow through the system.

Figure 2 - SoC Blockset provides system-level simulation and benchmarking of SoC-targeted applicationsFigure 2 - SoC Blockset provides system-level simulation and benchmarking of SoC-targeted applications


Deploying to Hardware

Once algorithm correctness and performance has been validated, code generation with HDL Coder™ and Embedded Coder™ can produce HDL IP cores to run on RFSoC programmable logic and embedded C code to run on the processing system. By enabling code generation from algorithm models, the potential for errors being introduced from hand-coding is eliminated. The code generated by these tools is both human-readable and traceable to source models, enabling workflows that can satisfy DO-178 and DO-254 objectives, among others.

In addition to HDL IP Core generation from models, reference application hardware subsystems and IP blocks are available for 5G, LTE, and other wireless applications from Wireless HDL Toolbox™, as used by RF Pixels when developing their mmWave test platform.


Verifying the Final Implementation

For verification of hardware implementation, HDL Verifier™ gives programmers the ability to verify RTL through co-simulation with MATLAB and Simulink test benches and test and debug on RFSoC hardware using MATLAB to access on-board memory.


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