UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 

Xilinx Introduces the Industry’s First Configurable Integrated SD-FEC— Leading to Higher Throughput with Lower Power

Xilinx Employee
Xilinx Employee
0 0 8,744

By Ambrose Finnerty, Xilinx DSP Technical Marketing Management

 

Maintaining transmission reliability in both Wireless and Cable data communications is a fundamental requirement for a quality solution. A key building block in these systems is a high-performance soft-decision forward error correction (SD-FEC) function required in both the transmit (encoder) and receive (decoder) paths.   

 

wp498_01.png

 

Figure 1: Typical Data Communication System

  

With ever increasing data bandwidths, seen for example with 5G New Radio (5G NR) and Data Over Cable Service Interface Specification 3.1 (DOCSIS 3.1), these systems have considerable data throughput needs that the SD-FEC blocks must be able to process efficiently.

 

Xilinx Introduces the Industry's First Integrated and Configurable (SD-FEC) IP Block

These SD-FEC functions have commonly been implemented in the programmable logic of high performance FPGAs. As the system requirements are pushed further to support multi-gigabit rates, performance, power, and cost have become key design factors. Soft implementation of these functions can be suboptimal compared to an integrated solution.

 

With this in mind, Xilinx has introduced the industry’s first integrated and configurable SD-FEC IP block enabling:

  • Alleviation of performance and throughput bottlenecks → ~3Gb/s peak LDPC decode throughput
  • Large reduction in resources → Savings of ~100k LUTs per SD-FEC instance
  • Massive power savings → 80% power reduction by moving to an integrated solution

 

wp498_05.png

 

Figure 2: Power Comparison of Integrated SD-FEC versus Soft LDPC Decoder

 

Example Applications that Benefit from Integration of the SD-FEC Function

As already pointed out, the ASIC-like SD-FEC block achieves greater throughput, lower latency, and lower power than a soft implementation. The ability to support Turbo decoding for Long-Term Evolution (LTE) and LTE-A applications make it a low-power solution for 4G and pre-5G systems.

 

With low-density parity check (LDPC) support for both decode and encode, it is possible to support applications like 5G baseband and backhaul platforms in the wireless market. In addition to the RF-ADCs/DACs found in the Zynq UltraScale+ RFSoC (ZU28DR) family, the SD-FEC provides an attractive solution for remote PHYs in the DOCSIS 3.1 standard.

 

To learn more on the specifics of Xilinx’s integrated SD-FEC in the Zynq UltraScale+ RFSoC and how you can leverage the power and throughput advantages, please take 10 minutes to read the following white paper outlining the block-level capabilities and benefits.