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Adaptable Advantage Blog

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Adaptable Advantage Blog

Xilinx Employee
Xilinx Employee

When was the last time you looked at a screen? Okay, that was a trick question, because unless you’re in the tree-killing business or your name is Moses and you have an affinity for stone tablets, you’re looking at one right now. You don’t have to be in a Dire Straits music video to realize screens are everywhere these days. As automation increases in factories, in vehicles, and in hospitals, screens are the best way to keep tabs on what’s happening. Real-time status is critically important. Here are a few examples: a hospital patient monitor, outlier notification on an operator panel, and fuel consumption analytics from a locomotive.

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Xilinx Employee
Xilinx Employee

Xilinx and AWS have been collaborating to bring AWS Greengrass to Zynq® UltraScale+™ MPSoC devices and Amazon FreeRTOS (a:FreeRTOS) to Zynq-7000 devices, helping developers accelerate Industrial IoT (IIoT) solutions. The combination of Xilinx’s scalable, secure, and adaptable hardware platform technologies combined with AWS technologies for secure connectivity, cloud-based system management, and a rich portfolio of AWS IoT Cloud Services provides a foundation for IIoT developers to build upon.

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Xilinx Employee
Xilinx Employee

No RTL experience is required for this webinar! You will see how to rapidly prototype virtually any embedded design with external peripherals in minutes. Additionally, you will learn all the benefits of building Xilinx embedded processors including real-time deterministic processing and functional safety.

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Xilinx Employee
Xilinx Employee

Learn how to take advantage of the rich feature set of Zynq® UltraScale+™ MPSoCs with Hardent’s “Getting Started with Xilinx Zynq UltraScale+ MPSoCs” training webinar on November 13!

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Xilinx Employee
Xilinx Employee

On the second day at XDF 2018, Peter Frey, Xilinx Principal Software Product Application Engineer, provided an overview of the methods for accelerating an SDAccel design to help users get the most computation and acceleration from their designs.

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Xilinx Employee
Xilinx Employee

Abhishek Ranjan and Mohit Kumar from BigZetta Systems gave a very interesting presentation about the Apache Hadoop Map-Reduce framework and how they were able to accelerate it using Amazon Web Services (AWS) F1 instances.

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Xilinx Employee
Xilinx Employee

As previously noted in our FPL 2018 recap blog Xilinx had a very strong presence at FPL. The Xilinx Silicon Architecture team had many people who presented / published papers at FPL. We are excited to share these great papers published at FPL. Check them out!

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Xilinx Employee
Xilinx Employee

On the first day at XDF 2018, AWS gave a presentation on how to accelerate development, test, and deployment of FPGA-accelerated applications on AWS EC2 F1.

Kris King, AWS Design Verification Manager – Silicon Optimization, made five major announcements:

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Xilinx Employee
Xilinx Employee

Our developer community and everyone who joined us at Xilinx Developer Forum (XDF) Silicon Valley helped to make it our biggest, most successful developer event yet. XDF Silicon Valley brought together over 1,100 attendees from 24 countries for 80+ sessions and 40+ exhibitor demos. If you weren’t able to make it to XDF, we've got you covered. Xilinx reporters were everywhere to capture the highlights. We're going to post recap blogs for the next few weeks. Today is all about Versal AI Engine.

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Xilinx Employee
Xilinx Employee

We just finished 2018 Xilinx Developer Forum (XDF) Silicon Valley in San Jose, CA. XDF is a pivotal event for Xilinx because it connects developers to the deep expertise of Xilinx engineers, partners, and industry leaders. Before we give full coverage of 2018 XDF, let's recap what happened at the 2018 Field Programmable Logic & Applications conference.

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Xilinx Employee
Xilinx Employee

The Zynq UltraScale+ RFSoC revolutionized RF and wireless systems by introducing a programmable device with integrated RF data converters. Traditionally, the RF design world and digital design worlds were separated - only connected by a JESD204 interface. Neither digital nor RF engineers needed or cared much about the other domain. That has changed now that the Zynq UltraScale+ RFSoC has brought them together in one device; increasingly, it will be critical that RF engineers understand more of the digital domain and vice-versa. To help engineers learn to work across both domains, Avnet and Mathworks are introducing a series of training and tools that target the Zynq UltraScale+ RFSoC.

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Xilinx Employee
Xilinx Employee

Avnet has recently released a new member of the UltraZed family System On Module (SOM). The UltraZed-EV features a Zynq® UltraScale+™ MPSoC XCZU7EV, joining the previously released UltraZed-EG, which is based on EG devices. The XCZU7EV is the largest of the EV devices. With 504K logic cells, 27.0Mb of UltraRAM, and 1,728 DSP slices, the XCZU7EV on the UltraZed-EV is ideally suited for multimedia applications!

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Xilinx Employee
Xilinx Employee

I am a coffee connoisseur and visit the coffee kiosk twice a day, so naturally, I really appreciate the reward system that the cafeteria offers. The only problem was that I kept losing my reward cards (ugh!). I asked around and learned that others shared a similar experience. At the same time, our company launched an internal competition to showcase the power of Zynq UltraScale+ MPSoC — so I used this opportunity to utilize the Xilinx ecosystem to come up with a solution.

 

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Xilinx Employee
Xilinx Employee

With complex network switches, also known as managed Ethernet switches, if you aren’t sure if you need one, you probably don’t. But truthfully, there are a lot of great features that managed Ethernet switches offer. And, if you're dealing with things that can never, ever, ever, never, ever, never fail—things like, hello, the electrical grid, or the plane you are sitting in, factories with high-speed robots and the like, they are mandatory features. Snooping for cybersecurity, reserving bandwidth for critical data, customized network setup and partitioning, fancy routing, redundancy to be fail-safe, and many other features typically come as part of the package with these complex network switches.

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Xilinx Employee
Xilinx Employee

In my previous blog post we discussed why proper planning is needed is for resets. Let us continue the discussion. In this blog we will examine techniques for combining multiple resets, sequencing resets across hierarchies and clock domains, the different types of flops available in Xilinx FPGAs and finally we will look at a few tips and tricks for handling resets in Vivado.

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Xilinx Employee
Xilinx Employee

Do you often find yourself facing timing closure challenges? Get ready to improve your productivity by learning the top best practices and techniques needed to achieve faster timing closure!

 

Xilinx Authorized Training Provider Hardent will be presenting a free webinar on Tuesday, September 11 titled “Achieve Faster Timing Closure in the Vivado Design Suite with the UltraFast Design Methodology”.

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Xilinx Employee
Xilinx Employee

2017 Flash Memory Summit was all about a new industry standard - NVMe-over-fabrics technology. This year at the Summit, data-centric computing overshadowed all other themes, dominating the entire show. While data-centric acceleration is not a new concept, it has transitioned from a research topic to a deployment topic - Xilinx, its partners, and other industry players have launched production-grade solutions that accomplish compute at the storage node with accelerators that offload the overwhelmed CPU.

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Xilinx Employee
Xilinx Employee

Zynq UltraScale+ RFSoC is a definitive breakthrough technology for the industry, providing the first integrated multi-gigabit sampling ADC and DAC capability with an FPGA fabric for full radio digital front-end solutions. This is a paradigm shift for system designers that enables smaller board footprints, lower system power, and simplified development for RF-class applications.

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Xilinx Employee
Xilinx Employee

The integration of direct RF-sampling data converters with Xilinx’s Zynq UltraScale+ RFSoC technology offers the most flexible, smallest footprint, and lowest power solution for a wide range of radio applications.

 

Webinar Date: September 11, 2018 

Time: 10 AM EDT (7 AM PDT) 

Duration: 1 hour

Presented by: EBV Elektronik and Xilinx, Inc.

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Xilinx Employee
Xilinx Employee

Introduction

Today's designs are really complicated with many clocks domains, embedded processors, IPs, complex state machines and sometimes even HLS tool generated RTL from high level languages like C/C++. This complexity is exacerbated by many types of resets - processor, system, core, software and IP resets. Further complicating the reset architecture is the choice of synchronous and asynchronous resets, active high and active low resets which makes RTL coding style complicated too. Unfortunately, reset architecture is not thought about early in the design cycle leading to every designer deciding the fate of resets in their blocks which results in a reset strategy that is ad-hoc and poorly planned and implemented leading to many iterations, debug and sometimes even product recalls.

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Xilinx Employee
Xilinx Employee

element14 is an online community that provides helpful tips and support for your latest project challenge. The community comprises engineers, manufacturers, innovators, and top experts who discuss technical challenges and products. They launched their professional development training project about a year ago after hearing members discuss the challenges of designing with PLDs—especially the steep learning curve. One of their latest projects, the Path to Programmable, trains five element14 members, who will, in turn, blog about their learning experiences—allowing others to more easily develop projects using programmable devices. The trainees are provided with free FPGA/SoC training modules and lab exercises and will then build a project with the Avnet MiniZed™ development board.

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Xilinx Employee
Xilinx Employee

Maintaining transmission reliability in both Wireless and Cable data communications is a fundamental requirement for a quality solution. A key building block in these systems is a high-performance soft-decision forward error correction (SD-FEC) function required in both the transmit (encoder) and receive (decoder) paths.


With ever increasing data bandwidths, seen for example with 5G New Radio (5G NR) and Data Over Cable Service Interface Specification 3.1 (DOCSIS 3.1), these systems have considerable data throughput needs that the SD-FEC blocks must be able to process efficiently.

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Xilinx Employee
Xilinx Employee

This year, Flash Memory Summit (FMS) will highlight Non-Volatile Memory Express (NVMe), Non-Volatile Memory Express over Fabrics (NVMe-oF), Persistent Memory, advanced memory technologies, and key Open Source software topics. Xilinx, the leader in production-ready Storage Array to Host Connectivity, will exhibit its next-generation flash storage solutions across ecosystems, partners, and customers. 

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Xilinx Employee
Xilinx Employee

Functional Safety is the study of methods and measures to reduce risk of harm to people and equipment when machines malfunction or when their operating environment is interrupted. Thinking of the 2018 FIFA World Cup that just ended, if we apply this to a game of football, referees have the ability and power to halt a game when they feel a violation occurs, but don’t always see everything and don’t always make the right call.

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Xilinx Employee
Xilinx Employee

If you are someone that wonders, with a healthy dose of cynicism, why seemingly everything is touting as being smart and connected these days, you might ask yourself, “Does that really need to be connected?” (I’m looking at you Bluetooth toothbrush with companion app—I manage to brush my teeth twice a day and scrub them all quite well without your help, thank you very much.) The actual answer is found in human psychology, not technology—or at least it was for me (cue flashback music): in the spring of 2011, Wired Magazine published an article on feedback loops, and not the kind you use in designing latches and flip-flops.

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Xilinx Employee
Xilinx Employee

Xilinx has introduced the new Zynq UltraScale+ RFSoC ZCU111 Evaluation kit to enable RF-class analog design evaluation, bringing this disruptive technology to the masses to try for themselves. This kit is the first of its kind – featuring a Zynq UltraScale+ RFSoC, which integrates multi-gigabit ADC and DAC sampling capability with FPGA logic.

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Xilinx Employee
Xilinx Employee

Sometimes, we get situations reported, where the timing numbers for individual elements during Vivado STA do not match the timing numbers shown in the Simulation SDF file, also generated by Vivado.

This article tries to explain various possible reasons why this discrepancy might appear, and how to interpret/reconcile them.

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Xilinx Employee
Xilinx Employee

Have you ever noticed while streaming Netflix videos, sometime the video blurs and then returns to high quality very quickly? Do you know what Netflix did in-between those few seconds? Along with adaptive bitrate streaming, it is basically continuously scanning for best CDN(Content Delivery Network) servers that can deliver data-packets faster.

Netflix may have mastered this but techniques to deliver large amount of data without any interruption have been around for few years now. For example, at Xilinx, we have been using Web Installer with such features that enables faster downloads without any interruptions.

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Xilinx Employee
Xilinx Employee

Configurable Reporting - Xilinx Marketing - Xilinx PPG Enterprise Wiki

Converging a design can be tricky.  Usually when you push to solve one problem, changes ripple to other parts of your design and inevitably, other issues pop up.  In 2017.3 we are introducing a new feature that may help you solve this problem.  It’s called configurable reporting. 

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Xilinx Employee
Xilinx Employee

Partial Reconfiguration involves loading configuration data into an active running design.  While there are some safeguards built into the silicon and bitstreams, such as the Device ID that ensures the correct part is targeted, there are techniques that must be understood and implemented as part of the user’s design.  Designers should follow these recommendations to ensure that partial reconfiguration is done safely and predictably.

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