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Adaptable Advantage Blog

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Adaptable Advantage Blog

Xilinx Employee
Xilinx Employee

SoCs are becoming more heterogeneous, with multiple CPU clusters and special-purpose accelerators. As a result, asymmetric multiprocessor (AMP) systems need to be able to run different operating environments side-by-side on the same device. Until now, however, there has been no standard shared memory scheme for the configuration and interaction between these environments. By creating standards and open source frameworks, the OpenAMP project simplifies the creation of these mixed systems. Becoming a Linaro Community Project enables a more formal collaborative approach to driving much needed standardization.

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Xilinx Employee
Xilinx Employee

I work a lot with the PYNQ framework as you will see from my Hackster projects and of course previous Chronicles.

One of the most interesting aspects of the PYNQ framework is the ability it gives us to interface quickly and easily with new sensors, actuators and devices.

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Xilinx Employee
Xilinx Employee

Before you read on, we had our first sold out event in San Jose. Registrations are open for three more upcoming event locations worldwide!

What is XSWG, and how is it going to help protect Industrial and Healthcare IoT assets?

 

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Xilinx Employee
Xilinx Employee

Since the announcement of the Versal ACAP at XDF18, there has been great interest in the software environment which developers will use to leverage Versal ACAP and its vast capabilities.

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Xilinx Employee
Xilinx Employee

Last week, we looked at how we could work with loops in our HLS source code, exploring how we can flatten, merge and unroll loops.

This week, we are going to look at how we can work with the HLS analysis perspective, so we can understand where our optimizations will have the best impact in our HLS source.

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Xilinx Employee
Xilinx Employee

When we write code intended for HLS implementations, we tend to implement repetitive algorithms that process blocks of data — for example, signal or image processing.

As such, our HLS source code in either C or C++ tends to include several loops or nested loops. When it comes to optimizing, performance loops are one on the places we can start exploring optimization.

By default, HLS loops are kept rolled. This means that each iteration of the loop uses the same hardware. Of course, this provides the worst performance as each iteration is sequential.

Let’s take a simple accumulator, as shown below.

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Xilinx Employee
Xilinx Employee

5G is effectively reshaping wireless infrastructure and will provide a seamless solution for mobile and fixed communications, streaming video services, security monitoring, smart appliances, and even autonomous vehicles. This transformation, already underway, will change our daily lives. Today, Xilinx is at the forefront of 5G, offering a unique solution to engineers for exploration and validation of 5G systems. The Zynq® UltraScale+™ RFSoC has a proven track record as an ideal component in both 5G and other wireless systems, and Xilinx offers the ZCU111 Evaluation board to facilitate rapid prototyping and development.

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Xilinx Employee
Xilinx Employee

Can you see something moving at 2.5 million miles an hour? For the Fermi Gamma-ray Space Telescope, it’s no problem. And when the FGST captured the pulsar PSR J0002+6216 (J0002 for short) shooting through Cassiopeia at the same speed, astronomers were able to trace its path back to the supernova where it was formed, about 6,500 light-years away.

Like the other incredibly powerful telescopes instrumental in capturing the clearest image of a black hole the world has ever seen, the FGST represents decades of space-age engineering. It also represents the frontier of open source real-time technology, supported by a Real-Time Executive for Multiprocessor System (RTEMS), the same technology that DornerWorks has recently ported to the Xilinx Zynq UltraScale+ MPSoC.

 

 

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Xilinx Employee
Xilinx Employee

Block RAMs (BRAM) are one of the key building blocks within our programmable logic designs. They are used for a range of applications from the ROM to FIFOs, and many stops in between.

Of course, one of the most popular applications of BRAMs is to act as data and instruction memories for our embedded processing solutions, e.g. MicroBlaze, or Arm Cortex-M1 and M3.

While it would be nice to get our software correct first time, unless it is very simple, it rarely happens. As such we need several design iterations, if each iterations needs to re-run the implementation to update the BRAM contents the time between tests is considerable. Although we can use JTAG debugging for some flows easily, e.g. MicroBlaze, there are use cases where we cannot, like when working with Arm cores without a DAP or separate JTAG.

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Xilinx Employee
Xilinx Employee

Silicon Carbide (SiC) has gone from exotic to the mainstream with Tesla and other EVs’ adoption of the technology over the past five years. It’s no wonder because SiC solves several engineering challenges.

One of the main challenges in power electronics research is the rapid development of new topologies, e.g., modular multilevel converter (MMC). Even if new topologies promise better performance, with an increased number of states and possible switching combinations, they also require an increased computational complexity to drive them.

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Xilinx Employee
Xilinx Employee

One of the great things about programmable logic is its ability to free us from the sequential world that limits software performance.

Recent years have seen the introduction and adoption of tools such as High-Level Synthesis (HLS), SDAccel and SDSoC. These tools enable us to use higher level languages such as C, C++ and OpenCL to develop programmable logic-based solutions. Not only freeing us from the sequential SW world, but also opening up programmable logic to new users outside those of the traditional logic designer.

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Xilinx Employee
Xilinx Employee

Are you planning to attend the Xilinx Security Working Group 2019? Act fast! No-charge registration is almost sold out for sessions in San Jose and Munich, featuring Industrial and Healthcare IoT security sessions!

Watch a video from Xilinx on an effective Cyber Attack defense solution for your Healthcare or Industrial ‘Neighborhood!’

Before you read on, four worldwide events are now open for registration, with San Jose and Munich locations featuring sessions on Industrial and Healthcare IoT security. Register today!

 

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Xilinx Employee
Xilinx Employee

Several times in this series we have looked at working with I2C and SPI in both bare metal and Linux (for example spidev). These interfaces are great for interfacing with sensors and displays. So it stands to reason we want to use these interfaces in our PYNQ and Python Applications.

In this blog we are going to examine how we can use PYNQ(2v4) running on the Ultra96 to interface with I2C and SPI peripherals connected via the Click Mezzanine. 

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Xilinx Employee
Xilinx Employee

One major trend we’ve seen in the market is the growing number of ASIC and SoC design starts in AI, 5G, autonomous driving, and hyperscale data centers. In those applications, whole systems are getting more complex as new chip architecture and integrated software are evolving. Another trend is that prototyping is rapidly growing as software developers and system designers want to test with real I/O traffic before their own silicon devices are available.

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Xilinx Employee
Xilinx Employee

A significant number of my clients’ projects, for which I design the SoCs, FPGAs and boards, need to communicate with remote sensors or other remote equipment. While there is more to interfaces such as Time Sensitive Networking and CAN, legacy standards like RS485 and RS422 still remain very popular. RS485 and RS422 are used in a range of applications from industrial control to aircraft / vehicle electronics, satellites and home / building automation. In short, it is an interface we need to now how to work with as electronic / SoC / FPGA designers.

RS422 and RS485 are popular as they can be used to interface with remote devices and sensors down either PCB backplanes or across long cable runs of up to 1,200 meters (although the data rate drops with distance from as high as 35 Mbps to 100 Kbps). The differential nature of the signaling, also provides significant noise immunity, and unlike LVDS, they can be easily electrically isolated.

Another reason RS485 and RS422 are popular is thanks to the simplicity with which we can implement an interface. Often, all we require is a UART to transfer bytes of data — of course, we do need a data link layer (and perhaps higher layers) to transfer data successfully between nodes and use it in the application.

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Xilinx Employee
Xilinx Employee

One of the most critical bottlenecks in building hardware architectures for complex datapath workloads is the speed of the memory subsystem.  With the two latest additions to the Alveo™ accelerator card portfolio, the Alveo U50 and Alveo U280, we set out to eliminate that bottleneck by integrating high bandwidth memory gen2 (HBM2) into each of them. HBM2 is stacked DRAM memory in-package to shrink the power and PCB footprint but provides astounding memory bandwidth of 460GB/s. This represents a memory technology that delivers enough memory bandwidth to eliminate the memory bottlenecks seen in complex compute and data intensive workloads and fully unlock the incredibly parallel capability of FPGAs.

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Xilinx Employee
Xilinx Employee

RapidWright is a tool from Xilinx Research Labs which enables users to manipulate both the synthesized netlist and implementation of Seven Series and up FPGAs and SoCs.
While not a Xilinx official tool RapidWright enables improved Quality of Result (QoR) and productivity. These improvements are provided by RapidWright’s use of modular implementation, overlay and shells.
On its own RapidWright is not able to implement designs, for that we still use Vivado. To enable this close working relationship communication between Vivado and RapidWright takes place using Design Check Points.

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Xilinx Employee
Xilinx Employee

A few weeks ago, I attended the Xilinx Worldwide Sales Conference. Besides the opportunity to stay in a hotel where part of the Arnold Schwarzenegger film True Lies was filmed, this was a great opportunity to get hands on with new tools and boards in a number of lab sessions.

One of my favourite labs was the PYNQ RFSoC lab which I thought really demonstrated the RFSoC and its capabilities. This lab outlined not only the RF converter capabilities but also those of the SD FEC and even outlining how python can be used for digital signal processing on the Processing System (PS). Of course, the lab swiftly followed up with how the DSP algorithm could be accelerated using PYNQ and programmable logic overlays.

I was happy to see the inclusion of these labs in the latest PYNQ V2.4.1 release for the ZCU111. So, I thought I would dig out my ZCU111 and rerun the lab and share some of the most interesting results. 

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Xilinx Employee
Xilinx Employee

From our friends at Cyber Defense Magazine, here are a few notable cybersecurity statistics for 2019:

  1. In most cases, it takes half a year to detect a data breach
  2. Over 75% of the healthcare industry has been infected with malware over the last year
  3. 95% of cybersecurity breaches are due to human error—phishing attacks are the most common cybersecurity attack
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Xilinx Employee
Xilinx Employee

There are several different ways in which we can implement our design in programmable logic e.g. RTL, HLS, SDSoC & SDAccel and over the years I have looked at most of these for this blog or my hacker projects.

One method of programmable logic development we have not looked at is Model Composer, which enables a model based design flow. 

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Xilinx Employee
Xilinx Employee

In last week's blog, we set up the processing system (PS) and the programmable logic (PL) to be able to output live video using the DisplayPort Controller.

In this blog, we are going to create the SW that is necessary to output a test pattern generated in the PL on the screen.

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Xilinx Employee
Xilinx Employee

Achieving repeatable and reliable timing closure is every FPGA designer’s ultimate goal.

Hardent, a Xilinx Authorized Training Provider (ATP), is now offering a new 3-day advanced timing constraints training course designed to equip you with all the skills you need to achieve faster timing closure for your next design. 

Over 3 days of learning, your trainer will guide you through the Xilinx recommended process to improve design performance and reliability, and illustrate how to reduce design and implementation time by following these guidelines.

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Xilinx Employee
Xilinx Employee

Manuel Uhm, Director of Silicon Marketing at Xilinx, spoke with Signals & Bits about Xilinx’s new Versal™ ACAPs. Manuel walks through the motivation behind the ACAP and Xilinx’s vision to reach all types of developers. He then describes the Versal portfolio, all device series, and how each addresses a specific set of applications—ranging from AI in the cloud to edge systems.

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Xilinx Employee
Xilinx Employee

Many of the projects I work on for clients are based on embedded vision and image processing applications. One of the things I like about these projects is I get to see the results, very visibly, and hopefully see these improve as the project matures.

When it comes to displaying the image, there are several potential standards which can be used. However, if I am using a Zynq MPSoC device, I often try to use the DisplayPort Controller in the PS, as it is both very powerful and convenient.

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Xilinx Employee
Xilinx Employee

Many of the FPGAs and SoCs I design for clients are used in high reliability / mission critical systems, across a range of applications including automotive, defense, aerospace, and space.

This means I want to ensure any errors which might occur in the system can be either tolerated or avoided.

Of course, creating a mission critical system is a holistic task that must consider the system architecture, hardware design and programmable logic design. Before we even start thinking about the task which is verification, analysis and certification.

However, as logic designers, we should be familiar with capabilities provided internally within programmable logic that help us avoid and tolerate errors.

One such capability is the support for Error Correcting Codes (ECC) on Block RAMs enabling a single bit error to be corrected and a double bit error detected.

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Xilinx Employee
Xilinx Employee

Xilinx’s new streaming QDMA (Queue Direct Memory Access) shell platform, available on Alveo™ accelerator cards, provides developers with a low latency direct streaming connection between host and kernels. The QDMA shell includes a high-performance DMA that uses multiple queues optimized for both high bandwidth and high packet count data transfers.

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Xilinx Employee
Xilinx Employee

What do you associate with the word “logic”? If you are a “Trekkie,” you’ll probably respond with Vulcan philosophy: It’s the absence of everything that influences a result in an unpredictable way.

Logic is the foundation of Xilinx, and adaptability of logic makes our approach unique. FPGAs as well as SoCs with programmable logic come with an architecture that’s made for determinism. Xilinx’s Center of Excellence for Safety and Security continuously innovates ways to optimize Functional Safety designs with superior device architectures, design flows, and processes. Sharing the results of this innovation generates a good enough reason for a two-day get together with experts from leading companies who create functionally safe products for industrial automation, automotive, transportation, energy, and aerospace & defense.

 

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Xilinx Employee
Xilinx Employee

Over the last two blogs we have examined Inter Processor Communication (part one and part two) between a Zynq and a MicroBlaze. We will wrap up this mini series on IPC with an exploration of mutual exclusion or mutexes it is more commonly known.

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Xilinx Employee
Xilinx Employee

In last week’s blog, we examined the hardware build required in Vivado to implement Mailboxes and MUTEXs for Inter Processor Communication (IPC).

Now, we are going to look at how we can transfer data from one processor to the other using the Mailbox.

Remember, in this system we are using one of the Zynq Processing Systems (PS) A9 cores and a MicroBlaze in the programmable logic (PL).

Both the processors are connected to the Mailbox using AXI, as such we can send and receive messages with ease using the provided APIs in the board support package (BSP).

Exporting the design from Vivado to Xilinx SDK will import the hardware specification in to SDK. Examining the HDF file in the hardware project will show both the MicroBlaze and the Cortex-A9 memory map.

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Xilinx Employee
Xilinx Employee

Let’s talk about data. The amount of data produced is exploding and our existing infrastructure is struggling to keep up. We are seeing industrial, vision, and healthcare equipment manufacturers getting out in front of this trend by working more closely with Xilinx. Why, you ask? Smart factory, surveillance, and hospital assets contribute heavily to the data explosion, and these companies and their customers want to figure out a way to manage data economically and securely. Xilinx’s heterogeneous and scalable SoCs address today’s and tomorrow’s needs!

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