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Adaptable Advantage Blog

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Adaptable Advantage Blog

Xilinx Employee
Xilinx Employee

Last week, we looked at how we could create a virtual machine that would enable us to accelerate Vitis applications. This week, we are going to look at how we can create the hardware element of this Vitis platform.

To do this we will be using Vivado — the board I am going to target is the Ultra96 — and we will need the board files which can be obtained here.

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Xilinx Employee
Xilinx Employee

Demand for sensor fusion at the edge is exponentially increasing. Edge devices are being asked to do more than ever before, while still being cost-effective to deploy. Most low-cost solutions lack the processing power and flexibility to keep up with advancing Image Signal Processing (ISP) requirements and an ever-increasing number of sensors. Further, most image sensors available are designed for specific applications in high volume products like cell phones, making it difficult to apply them in your environment—increasing the need for ISP at the edge in industrial and automotive applications.

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Xilinx Employee
Xilinx Employee

One of the great things about Vitis is it enables us to accelerate our applications from the sequential software world into the parallel programmable logic world.

Of course, when we perform acceleration, we achieve an increase in not only performance but also determinism.

To accelerate applications using Vitis we need to use a Linux Machine which has the following requirements.

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Xilinx Employee
Xilinx Employee

Over the last few weeks we have looked at Vitis (P1, P2), which provides us with the ability to accelerate and create embedded applications.

To create programmable logic kernels, the Vitis V++ Compiler is capable of compiling OpenCL, C/C++ and RTL in to Xilinx Object (.xo) file and then linking these into the Xilinx binary (.xclbin) for the programmable logic.

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Xilinx Employee
Xilinx Employee

Digilent’s new ZedBoard advanced image processing kit, starting at $669, is an affordable solution for embedded vision system development. The base kit features a ZedBoard with a Zynq®-7000 SoC Z7020-CLG484 device, dual-cam Pcam 5C, and a Pcam adapter. Each 5C Pcam module is a 5MP color image sensor, with configurable image processing functions. Upgrade to a quad-cam Pcam 5C for an additional $50.

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Xilinx Employee
Xilinx Employee

A deep dive look at the Xilinx Vitis accelerated libraries.

Having looked last week at Vitis for embedded development systems, going forward we are going to be exploring how to use Vitis to accelerate our applications at the edge and in the cloud.

Before I do that, however, I think it would be a good idea to look at the libraries which are available to help us accelerate our applications.

 

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Xilinx Employee
Xilinx Employee

How to create our first Vitis project.

After its announcement at last month's Xilinx Developer Forum in San Jose, Vitis was made publicly available with Xilinx's 2019.2 release.

First things first as the unified SW environment Vitis replaces SDSoC, SDAccel and even SDK.

As a unified tool, Vitis enables us to develop for embedded targets just as we did with SDK or application acceleration e.g. SDSoC and SDAccel.

Depending upon what we wish to do, there are different installation requirements.

  • Application acceleration requires a Linux OS and 64 GB of memory for Alveo applications, 32 GB for Zynq / Zynq MPSoC.
  • Embedded development requires either Linux or Windows and 32 GB of memory.

Both require about a 100GB of hard disk space.

When Vitis is installed, we also install the complete Vivado Design Suite, which saves us having to install them separately.

In this blog, I am going to look at the embedded development such that we can create an application in Vivado and port it to the Vitis to debug and run just as we have before.

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Xilinx Employee
Xilinx Employee

Xilinx announced the Versal™ portfolio at XDF 2018. Versal ACAPs, fully software-programmable, heterogeneous compute platforms, combine Scalar Engines, Adaptable Engines, and Intelligent Engines to achieve dramatic performance improvements of up to 20X over today's fastest FPGA implementations—needed for today’s data center, wired network, 5G wireless, and automotive driver assist applications. This year at XDF 2019, we are showing actual demonstrations on Versal devices highlighting features that drive data center, edge, and wired and wireless communication applications. We invite you to check out Versal ACAP in action at XDF Europe, at the World Forum on 12-13, November 2019.

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Xilinx Employee
Xilinx Employee

Many of our MicroBlaze, Zynq and Zynq MPSoC applications are deployed in applications which require real time operation. Indeed many of these require hard real time capabilities where a failure to meet a deadline is seen as a failure of the system.

On popular real time operating system which is used on many aerospace, defense and space applications is RTEMS or Real Time Executive for Multiprocessor Systems.

RTEMS was originally developed in the 1980's as the Real Time Executive for Missile Systems and has been ported to many architectures including ARM, MIPS, MicroBlaze, PowerPC and of course SPARC.

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Xilinx Employee
Xilinx Employee

Last week I introduced how we can use PYNQ to access telemetry data on a boards power system, if it uses PMBus. In this article, we are going to look at how we can use the this capability in PYNQ to log and analyze power data.

The main element we will be using to do this is the DataRecorder contained within the PMBus package.

The DataRecorder provides the ability to stop, start and reset sampling on selected PMBus sensors. We can achieve fine grained control of the sampling period as we are able to define the sampling period when the DataRecorder is started.

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Xilinx Employee
Xilinx Employee

Within our FPGA and SoC designs we create many exciting applications from machine learning, to image and signal processing and industrial control.

However, without the ability to correctly power our devices we will not be able to run our FPGA and SoC-based applications. Modern FPGA and SoC are complex devices requiring low voltage rails at high currents, for the power designer there are several challenges in delivering these voltages within the tight tolerances at high current demands.

The solution to these challenges is to use PMICs or power management ICs such as the IRPS5401 and IRPS5401 that you will find on the Ultra96v2 boards.

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Xilinx Employee
Xilinx Employee

SoCs are becoming more heterogeneous, with multiple CPU clusters and special-purpose accelerators. As a result, asymmetric multiprocessor (AMP) systems need to be able to run different operating environments side-by-side on the same device. Until now, however, there has been no standard shared memory scheme for the configuration and interaction between these environments. By creating standards and open source frameworks, the OpenAMP project simplifies the creation of these mixed systems. Becoming a Linaro Community Project enables a more formal collaborative approach to driving much needed standardization.

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Xilinx Employee
Xilinx Employee

I work a lot with the PYNQ framework as you will see from my Hackster projects and of course previous Chronicles.

One of the most interesting aspects of the PYNQ framework is the ability it gives us to interface quickly and easily with new sensors, actuators and devices.

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Xilinx Employee
Xilinx Employee

Before you read on, we had our first sold out event in San Jose. Registrations are open for three more upcoming event locations worldwide!

What is XSWG, and how is it going to help protect Industrial and Healthcare IoT assets?

 

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Xilinx Employee
Xilinx Employee

Since the announcement of the Versal ACAP at XDF18, there has been great interest in the software environment which developers will use to leverage Versal ACAP and its vast capabilities.

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Xilinx Employee
Xilinx Employee

Last week, we looked at how we could work with loops in our HLS source code, exploring how we can flatten, merge and unroll loops.

This week, we are going to look at how we can work with the HLS analysis perspective, so we can understand where our optimizations will have the best impact in our HLS source.

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Xilinx Employee
Xilinx Employee

When we write code intended for HLS implementations, we tend to implement repetitive algorithms that process blocks of data — for example, signal or image processing.

As such, our HLS source code in either C or C++ tends to include several loops or nested loops. When it comes to optimizing, performance loops are one on the places we can start exploring optimization.

By default, HLS loops are kept rolled. This means that each iteration of the loop uses the same hardware. Of course, this provides the worst performance as each iteration is sequential.

Let’s take a simple accumulator, as shown below.

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Xilinx Employee
Xilinx Employee

5G is effectively reshaping wireless infrastructure and will provide a seamless solution for mobile and fixed communications, streaming video services, security monitoring, smart appliances, and even autonomous vehicles. This transformation, already underway, will change our daily lives. Today, Xilinx is at the forefront of 5G, offering a unique solution to engineers for exploration and validation of 5G systems. The Zynq® UltraScale+™ RFSoC has a proven track record as an ideal component in both 5G and other wireless systems, and Xilinx offers the ZCU111 Evaluation board to facilitate rapid prototyping and development.

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Xilinx Employee
Xilinx Employee

Can you see something moving at 2.5 million miles an hour? For the Fermi Gamma-ray Space Telescope, it’s no problem. And when the FGST captured the pulsar PSR J0002+6216 (J0002 for short) shooting through Cassiopeia at the same speed, astronomers were able to trace its path back to the supernova where it was formed, about 6,500 light-years away.

Like the other incredibly powerful telescopes instrumental in capturing the clearest image of a black hole the world has ever seen, the FGST represents decades of space-age engineering. It also represents the frontier of open source real-time technology, supported by a Real-Time Executive for Multiprocessor System (RTEMS), the same technology that DornerWorks has recently ported to the Xilinx Zynq UltraScale+ MPSoC.

 

 

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Xilinx Employee
Xilinx Employee

Block RAMs (BRAM) are one of the key building blocks within our programmable logic designs. They are used for a range of applications from the ROM to FIFOs, and many stops in between.

Of course, one of the most popular applications of BRAMs is to act as data and instruction memories for our embedded processing solutions, e.g. MicroBlaze, or Arm Cortex-M1 and M3.

While it would be nice to get our software correct first time, unless it is very simple, it rarely happens. As such we need several design iterations, if each iterations needs to re-run the implementation to update the BRAM contents the time between tests is considerable. Although we can use JTAG debugging for some flows easily, e.g. MicroBlaze, there are use cases where we cannot, like when working with Arm cores without a DAP or separate JTAG.

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Xilinx Employee
Xilinx Employee

Silicon Carbide (SiC) has gone from exotic to the mainstream with Tesla and other EVs’ adoption of the technology over the past five years. It’s no wonder because SiC solves several engineering challenges.

One of the main challenges in power electronics research is the rapid development of new topologies, e.g., modular multilevel converter (MMC). Even if new topologies promise better performance, with an increased number of states and possible switching combinations, they also require an increased computational complexity to drive them.

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Xilinx Employee
Xilinx Employee

One of the great things about programmable logic is its ability to free us from the sequential world that limits software performance.

Recent years have seen the introduction and adoption of tools such as High-Level Synthesis (HLS), SDAccel and SDSoC. These tools enable us to use higher level languages such as C, C++ and OpenCL to develop programmable logic-based solutions. Not only freeing us from the sequential SW world, but also opening up programmable logic to new users outside those of the traditional logic designer.

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Xilinx Employee
Xilinx Employee

Are you planning to attend the Xilinx Security Working Group 2019? Act fast! No-charge registration is almost sold out for sessions in San Jose and Munich, featuring Industrial and Healthcare IoT security sessions!

Watch a video from Xilinx on an effective Cyber Attack defense solution for your Healthcare or Industrial ‘Neighborhood!’

Before you read on, four worldwide events are now open for registration, with San Jose and Munich locations featuring sessions on Industrial and Healthcare IoT security. Register today!

 

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Xilinx Employee
Xilinx Employee

Several times in this series we have looked at working with I2C and SPI in both bare metal and Linux (for example spidev). These interfaces are great for interfacing with sensors and displays. So it stands to reason we want to use these interfaces in our PYNQ and Python Applications.

In this blog we are going to examine how we can use PYNQ(2v4) running on the Ultra96 to interface with I2C and SPI peripherals connected via the Click Mezzanine. 

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Xilinx Employee
Xilinx Employee

One major trend we’ve seen in the market is the growing number of ASIC and SoC design starts in AI, 5G, autonomous driving, and hyperscale data centers. In those applications, whole systems are getting more complex as new chip architecture and integrated software are evolving. Another trend is that prototyping is rapidly growing as software developers and system designers want to test with real I/O traffic before their own silicon devices are available.

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Xilinx Employee
Xilinx Employee

A significant number of my clients’ projects, for which I design the SoCs, FPGAs and boards, need to communicate with remote sensors or other remote equipment. While there is more to interfaces such as Time Sensitive Networking and CAN, legacy standards like RS485 and RS422 still remain very popular. RS485 and RS422 are used in a range of applications from industrial control to aircraft / vehicle electronics, satellites and home / building automation. In short, it is an interface we need to now how to work with as electronic / SoC / FPGA designers.

RS422 and RS485 are popular as they can be used to interface with remote devices and sensors down either PCB backplanes or across long cable runs of up to 1,200 meters (although the data rate drops with distance from as high as 35 Mbps to 100 Kbps). The differential nature of the signaling, also provides significant noise immunity, and unlike LVDS, they can be easily electrically isolated.

Another reason RS485 and RS422 are popular is thanks to the simplicity with which we can implement an interface. Often, all we require is a UART to transfer bytes of data — of course, we do need a data link layer (and perhaps higher layers) to transfer data successfully between nodes and use it in the application.

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Xilinx Employee
Xilinx Employee

One of the most critical bottlenecks in building hardware architectures for complex datapath workloads is the speed of the memory subsystem.  With the two latest additions to the Alveo™ accelerator card portfolio, the Alveo U50 and Alveo U280, we set out to eliminate that bottleneck by integrating high bandwidth memory gen2 (HBM2) into each of them. HBM2 is stacked DRAM memory in-package to shrink the power and PCB footprint but provides astounding memory bandwidth of 460GB/s. This represents a memory technology that delivers enough memory bandwidth to eliminate the memory bottlenecks seen in complex compute and data intensive workloads and fully unlock the incredibly parallel capability of FPGAs.

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Xilinx Employee
Xilinx Employee

RapidWright is a tool from Xilinx Research Labs which enables users to manipulate both the synthesized netlist and implementation of Seven Series and up FPGAs and SoCs.
While not a Xilinx official tool RapidWright enables improved Quality of Result (QoR) and productivity. These improvements are provided by RapidWright’s use of modular implementation, overlay and shells.
On its own RapidWright is not able to implement designs, for that we still use Vivado. To enable this close working relationship communication between Vivado and RapidWright takes place using Design Check Points.

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Xilinx Employee
Xilinx Employee

A few weeks ago, I attended the Xilinx Worldwide Sales Conference. Besides the opportunity to stay in a hotel where part of the Arnold Schwarzenegger film True Lies was filmed, this was a great opportunity to get hands on with new tools and boards in a number of lab sessions.

One of my favourite labs was the PYNQ RFSoC lab which I thought really demonstrated the RFSoC and its capabilities. This lab outlined not only the RF converter capabilities but also those of the SD FEC and even outlining how python can be used for digital signal processing on the Processing System (PS). Of course, the lab swiftly followed up with how the DSP algorithm could be accelerated using PYNQ and programmable logic overlays.

I was happy to see the inclusion of these labs in the latest PYNQ V2.4.1 release for the ZCU111. So, I thought I would dig out my ZCU111 and rerun the lab and share some of the most interesting results. 

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Xilinx Employee
Xilinx Employee

From our friends at Cyber Defense Magazine, here are a few notable cybersecurity statistics for 2019:

  1. In most cases, it takes half a year to detect a data breach
  2. Over 75% of the healthcare industry has been infected with malware over the last year
  3. 95% of cybersecurity breaches are due to human error—phishing attacks are the most common cybersecurity attack
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