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The Coffee Conundrum: The Origins of Ultra96

by Xilinx Employee ‎09-18-2018 03:55 PM - edited ‎09-24-2018 05:10 PM

I am a coffee connoisseur and visit the coffee kiosk twice a day, so naturally, I really appreciate the reward system that the cafeteria offers. The only problem was that I kept losing my reward cards (ugh!). I asked around and learned that others shared a similar experience. At the same time, our company launched an internal competition to showcase the power of Zynq UltraScale+ MPSoC — so I used this opportunity to utilize the Xilinx ecosystem to come up with a solution.

 

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With complex network switches, also known as managed Ethernet switches, if you aren’t sure if you need one, you probably don’t. But truthfully, there are a lot of great features that managed Ethernet switches offer. And, if you're dealing with things that can never, ever, ever, never, ever, never fail—things like, hello, the electrical grid, or the plane you are sitting in, factories with high-speed robots and the like, they are mandatory features. Snooping for cybersecurity, reserving bandwidth for critical data, customized network setup and partitioning, fancy routing, redundancy to be fail-safe, and many other features typically come as part of the package with these complex network switches.

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In my previous blog post we discussed why proper planning is needed is for resets. Let us continue the discussion. In this blog we will examine techniques for combining multiple resets, sequencing resets across hierarchies and clock domains, the different types of flops available in Xilinx FPGAs and finally we will look at a few tips and tricks for handling resets in Vivado.

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Do you often find yourself facing timing closure challenges? Get ready to improve your productivity by learning the top best practices and techniques needed to achieve faster timing closure!

 

Xilinx Authorized Training Provider Hardent will be presenting a free webinar on Tuesday, September 11 titled “Achieve Faster Timing Closure in the Vivado Design Suite with the UltraFast Design Methodology”.

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2018 Flash Memory Summit Recap: The Data-Centric Era has Arrived

by Xilinx Employee ‎08-31-2018 09:18 AM - edited ‎09-04-2018 04:04 PM

2017 Flash Memory Summit was all about a new industry standard - NVMe-over-fabrics technology. This year at the Summit, data-centric computing overshadowed all other themes, dominating the entire show. While data-centric acceleration is not a new concept, it has transitioned from a research topic to a deployment topic - Xilinx, its partners, and other industry players have launched production-grade solutions that accomplish compute at the storage node with accelerators that offload the overwhelmed CPU.

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RF-Class Analog Design Must-Haves Now Available

by Xilinx Employee ‎08-28-2018 12:35 PM - edited ‎09-04-2018 04:50 PM

Zynq UltraScale+ RFSoC is a definitive breakthrough technology for the industry, providing the first integrated multi-gigabit sampling ADC and DAC capability with an FPGA fabric for full radio digital front-end solutions. This is a paradigm shift for system designers that enables smaller board footprints, lower system power, and simplified development for RF-class applications.

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The integration of direct RF-sampling data converters with Xilinx’s Zynq UltraScale+ RFSoC technology offers the most flexible, smallest footprint, and lowest power solution for a wide range of radio applications.

 

Webinar Date: September 11, 2018 

Time: 10 AM EDT (7 AM PDT) 

Duration: 1 hour

Presented by: EBV Elektronik and Xilinx, Inc.

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Demystifying Resets: Synchronous, Asynchronous other Design Considerations... Part 1

by Xilinx Employee ‎08-15-2018 03:01 PM - edited ‎08-21-2018 09:24 AM

Introduction

Today's designs are really complicated with many clocks domains, embedded processors, IPs, complex state machines and sometimes even HLS tool generated RTL from high level languages like C/C++. This complexity is exacerbated by many types of resets - processor, system, core, software and IP resets. Further complicating the reset architecture is the choice of synchronous and asynchronous resets, active high and active low resets which makes RTL coding style complicated too. Unfortunately, reset architecture is not thought about early in the design cycle leading to every designer deciding the fate of resets in their blocks which results in a reset strategy that is ad-hoc and poorly planned and implemented leading to many iterations, debug and sometimes even product recalls.

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element14 and the Path to Programmable

by Xilinx Employee ‎08-09-2018 04:17 PM - edited ‎09-04-2018 04:44 PM

element14 is an online community that provides helpful tips and support for your latest project challenge. The community comprises engineers, manufacturers, innovators, and top experts who discuss technical challenges and products. They launched their professional development training project about a year ago after hearing members discuss the challenges of designing with PLDs—especially the steep learning curve. One of their latest projects, the Path to Programmable, trains five element14 members, who will, in turn, blog about their learning experiences—allowing others to more easily develop projects using programmable devices. The trainees are provided with free FPGA/SoC training modules and lab exercises and will then build a project with the Avnet MiniZed™ development board.

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Maintaining transmission reliability in both Wireless and Cable data communications is a fundamental requirement for a quality solution. A key building block in these systems is a high-performance soft-decision forward error correction (SD-FEC) function required in both the transmit (encoder) and receive (decoder) paths.


With ever increasing data bandwidths, seen for example with 5G New Radio (5G NR) and Data Over Cable Service Interface Specification 3.1 (DOCSIS 3.1), these systems have considerable data throughput needs that the SD-FEC blocks must be able to process efficiently.

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Xilinx at Flash Memory Summit 2018

by Xilinx Employee ‎07-26-2018 05:10 PM - edited ‎09-04-2018 04:46 PM

This year, Flash Memory Summit (FMS) will highlight Non-Volatile Memory Express (NVMe), Non-Volatile Memory Express over Fabrics (NVMe-oF), Persistent Memory, advanced memory technologies, and key Open Source software topics. Xilinx, the leader in production-ready Storage Array to Host Connectivity, will exhibit its next-generation flash storage solutions across ecosystems, partners, and customers. 

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Breaking Down the Complexity of Functional Safety Design

by Xilinx Employee ‎07-19-2018 03:09 PM - edited ‎09-04-2018 04:49 PM

Functional Safety is the study of methods and measures to reduce risk of harm to people and equipment when machines malfunction or when their operating environment is interrupted. Thinking of the 2018 FIFA World Cup that just ended, if we apply this to a game of football, referees have the ability and power to halt a game when they feel a violation occurs, but don’t always see everything and don’t always make the right call.

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If you are someone that wonders, with a healthy dose of cynicism, why seemingly everything is touting as being smart and connected these days, you might ask yourself, “Does that really need to be connected?” (I’m looking at you Bluetooth toothbrush with companion app—I manage to brush my teeth twice a day and scrub them all quite well without your help, thank you very much.) The actual answer is found in human psychology, not technology—or at least it was for me (cue flashback music): in the spring of 2011, Wired Magazine published an article on feedback loops, and not the kind you use in designing latches and flip-flops.

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Xilinx has introduced the new Zynq UltraScale+ RFSoC ZCU111 Evaluation kit to enable RF-class analog design evaluation, bringing this disruptive technology to the masses to try for themselves. This kit is the first of its kind – featuring a Zynq UltraScale+ RFSoC, which integrates multi-gigabit ADC and DAC sampling capability with FPGA logic.

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Mismatch in Timing Numbers between SDF and STA

by Xilinx Employee ‎01-18-2018 12:11 PM - edited ‎01-19-2018 09:32 AM

Sometimes, we get situations reported, where the timing numbers for individual elements during Vivado STA do not match the timing numbers shown in the Simulation SDF file, also generated by Vivado.

This article tries to explain various possible reasons why this discrepancy might appear, and how to interpret/reconcile them.

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Best way to download Xilinx Design Tools

by Xilinx Employee ‎12-19-2017 01:36 PM - edited ‎12-19-2017 02:00 PM

Have you ever noticed while streaming Netflix videos, sometime the video blurs and then returns to high quality very quickly? Do you know what Netflix did in-between those few seconds? Along with adaptive bitrate streaming, it is basically continuously scanning for best CDN(Content Delivery Network) servers that can deliver data-packets faster.

Netflix may have mastered this but techniques to deliver large amount of data without any interruption have been around for few years now. For example, at Xilinx, we have been using Web Installer with such features that enables faster downloads without any interruptions.

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Configurable Reporting

by Xilinx Employee ‎10-26-2017 11:07 AM - edited ‎10-26-2017 11:12 AM

Configurable Reporting - Xilinx Marketing - Xilinx PPG Enterprise Wiki

Converging a design can be tricky.  Usually when you push to solve one problem, changes ripple to other parts of your design and inevitably, other issues pop up.  In 2017.3 we are introducing a new feature that may help you solve this problem.  It’s called configurable reporting. 

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Partial Reconfiguration involves loading configuration data into an active running design.  While there are some safeguards built into the silicon and bitstreams, such as the Device ID that ensures the correct part is targeted, there are techniques that must be understood and implemented as part of the user’s design.  Designers should follow these recommendations to ensure that partial reconfiguration is done safely and predictably.

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Partial Reconfiguration Design Flow – The Configuration Analysis Report

by Xilinx Employee ‎10-13-2017 01:05 PM - edited ‎10-13-2017 02:00 PM

One unique aspect of the Partial Reconfiguration (PR) design flow is that there are multiple versions of the design that must be implemented through place and route.  These different “configurations” have common static design results but differing modules within each Reconfigurable Partition (RP).  Designers must set up timing constraints and floorplans that account for these different modules that will be swapped on the fly.  It can be challenging

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In today's designs it is typical to have a large number of clocks that interact with each other. In order to ensure that Vivado optimizes paths that are critical, it is essential to understand how the clocks interact and how they are related – synchronous and asynchronous clocks.

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AXI Interface Debug Using IP Integrator

by Xilinx Employee ‎09-14-2017 03:13 PM - edited ‎09-15-2017 11:21 AM

IP Integrator users connect IP blocks to create complex system designs. These block-based designs are typically constructed at the interface level and interfaces usually contain multiple busses and a large number of individual signals. Therefore, in order to easily debug these designs in hardware, it is necessary to verify the design interface-level connectivity.

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Support for IP using "Standalone" .dcp Instead of .xci

by Xilinx Employee ‎09-14-2017 11:02 AM - edited ‎09-15-2017 10:56 AM

Beginning in 2017.1, we announced that xci and xcix files should be used for all Xilinx IP in our catalog.  This isn’t really new, we’ve actually been communicating that this is our primary recommendation for many years now.  And there are many important reasons for this.  The xci file is an xml file that captures all the configuration settings for the ip and more importantly points Vivado towards the plethora of files that are produced for ip; including - out of context synthesis, constraints, and simulation files.  The xci file is really how Vivado determines if the IP is “fully generated” or if there are any files missing.

 

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In the project flow, Vivado keeps track of dependencies. As you invoke a particular step, the tool ensures that the previous step is complete

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Terminology for IP Flow

by Xilinx Employee on ‎10-26-2016 04:54 PM

The Xilinx IP based flow uses terminology that is different from the terms used by typical RTL based designers.

As a result, we need to define certain terminology which might be unique to our IP Flow.

This blog article will attempt to demystify the terminology for flows related to IP.

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Adding soft IP Cores such as MicroBlaze Subsystems or DDR Controllers as part of the Update Region of a Tandem with Field Updates Design.

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Output Delay

by Xilinx Employee on ‎01-28-2016 01:55 PM

In this article, we will discuss the concept behind output_delay.

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Vivado allows for a portion of the design to be synthesized Out-Of-Context (OOC).

The basic idea with an OOC flow is that a part of the design is synthesized by itself.

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Constraining Asynchronous Clocks

by Xilinx Employee on ‎09-30-2015 02:40 PM

For asynchronous clocks, there are four ways to write the constraints.

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Time Borrowing in Latches

by Xilinx Employee on ‎08-28-2015 09:28 AM

Static Timing Analysis applies a concept called Time Borrowing for latch based designs.

This blog post explains time-borrowing, and is relevant to cases where your design has latches, and your timing report has time-borrowing.

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Ensuring Skew Control on Data Lines

by Xilinx Employee on ‎08-02-2015 10:44 PM

Sometimes, we might want a few signals to appear at more or less the same time time (i.e. the skew between these signals should not be beyond a certain limit).

A typical situation could be multiple bits of a bus, which should be arriving (almost) together.

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