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Adaptable Advantage Blog

Xilinx Employee
Xilinx Employee

In last week's blog, we examined how to install and use the open-source simulator GHDL. This week, we will expand the use of GHDL with an open-source verification framework for VHDL called UVVM.

UVVM or Universal VHDL Verification Methodology is a free and open-source verification framework created by the Norwegian company bitvis.

Funded in part by the European Space Agency (ESA), UVVM is one of the most powerful VHDL verification frameworks. Along with the framework for creating the test benches which includes scoreboards, alerts, logging, checking, transactions and more, UVVM also provides several VHDL Verification Components (VVC). These VHDL Verification Components provide users with a fast and easy method to implement standard interfaces like the ones listed below.  


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