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Adaptable Advantage Blog - Page 2

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Adaptable Advantage Blog - Page 2

Xilinx Employee
Xilinx Employee

This year, Flash Memory Summit (FMS) will highlight Non-Volatile Memory Express (NVMe), Non-Volatile Memory Express over Fabrics (NVMe-oF), Persistent Memory, advanced memory technologies, and key Open Source software topics. Xilinx, the leader in production-ready Storage Array to Host Connectivity, will exhibit its next-generation flash storage solutions across ecosystems, partners, and customers. 

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Xilinx Employee
Xilinx Employee

Functional Safety is the study of methods and measures to reduce risk of harm to people and equipment when machines malfunction or when their operating environment is interrupted. Thinking of the 2018 FIFA World Cup that just ended, if we apply this to a game of football, referees have the ability and power to halt a game when they feel a violation occurs, but don’t always see everything and don’t always make the right call.

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Xilinx Employee
Xilinx Employee

If you are someone that wonders, with a healthy dose of cynicism, why seemingly everything is touting as being smart and connected these days, you might ask yourself, “Does that really need to be connected?” (I’m looking at you Bluetooth toothbrush with companion app—I manage to brush my teeth twice a day and scrub them all quite well without your help, thank you very much.) The actual answer is found in human psychology, not technology—or at least it was for me (cue flashback music): in the spring of 2011, Wired Magazine published an article on feedback loops, and not the kind you use in designing latches and flip-flops.

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Xilinx Employee
Xilinx Employee

Xilinx has introduced the new Zynq UltraScale+ RFSoC ZCU111 Evaluation kit to enable RF-class analog design evaluation, bringing this disruptive technology to the masses to try for themselves. This kit is the first of its kind – featuring a Zynq UltraScale+ RFSoC, which integrates multi-gigabit ADC and DAC sampling capability with FPGA logic.

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Xilinx Employee
Xilinx Employee

Sometimes, we get situations reported, where the timing numbers for individual elements during Vivado STA do not match the timing numbers shown in the Simulation SDF file, also generated by Vivado.

This article tries to explain various possible reasons why this discrepancy might appear, and how to interpret/reconcile them.

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Xilinx Employee
Xilinx Employee

Have you ever noticed while streaming Netflix videos, sometime the video blurs and then returns to high quality very quickly? Do you know what Netflix did in-between those few seconds? Along with adaptive bitrate streaming, it is basically continuously scanning for best CDN(Content Delivery Network) servers that can deliver data-packets faster.

Netflix may have mastered this but techniques to deliver large amount of data without any interruption have been around for few years now. For example, at Xilinx, we have been using Web Installer with such features that enables faster downloads without any interruptions.

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Xilinx Employee
Xilinx Employee

Configurable Reporting - Xilinx Marketing - Xilinx PPG Enterprise Wiki

Converging a design can be tricky.  Usually when you push to solve one problem, changes ripple to other parts of your design and inevitably, other issues pop up.  In 2017.3 we are introducing a new feature that may help you solve this problem.  It’s called configurable reporting. 

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Xilinx Employee
Xilinx Employee

Partial Reconfiguration involves loading configuration data into an active running design.  While there are some safeguards built into the silicon and bitstreams, such as the Device ID that ensures the correct part is targeted, there are techniques that must be understood and implemented as part of the user’s design.  Designers should follow these recommendations to ensure that partial reconfiguration is done safely and predictably.

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Xilinx Employee
Xilinx Employee

One unique aspect of the Partial Reconfiguration (PR) design flow is that there are multiple versions of the design that must be implemented through place and route.  These different “configurations” have common static design results but differing modules within each Reconfigurable Partition (RP).  Designers must set up timing constraints and floorplans that account for these different modules that will be swapped on the fly.  It can be challenging

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Xilinx Employee
Xilinx Employee

In today's designs it is typical to have a large number of clocks that interact with each other. In order to ensure that Vivado optimizes paths that are critical, it is essential to understand how the clocks interact and how they are related – synchronous and asynchronous clocks.

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Xilinx Employee
Xilinx Employee

IP Integrator users connect IP blocks to create complex system designs. These block-based designs are typically constructed at the interface level and interfaces usually contain multiple busses and a large number of individual signals. Therefore, in order to easily debug these designs in hardware, it is necessary to verify the design interface-level connectivity.

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Xilinx Employee
Xilinx Employee

Beginning in 2017.1, we announced that xci and xcix files should be used for all Xilinx IP in our catalog.  This isn’t really new, we’ve actually been communicating that this is our primary recommendation for many years now.  And there are many important reasons for this.  The xci file is an xml file that captures all the configuration settings for the ip and more importantly points Vivado towards the plethora of files that are produced for ip; including - out of context synthesis, constraints, and simulation files.  The xci file is really how Vivado determines if the IP is “fully generated” or if there are any files missing.

 

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Xilinx Employee
Xilinx Employee

In the project flow, Vivado keeps track of dependencies. As you invoke a particular step, the tool ensures that the previous step is complete

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Xilinx Employee
Xilinx Employee

The Xilinx IP based flow uses terminology that is different from the terms used by typical RTL based designers.

As a result, we need to define certain terminology which might be unique to our IP Flow.

This blog article will attempt to demystify the terminology for flows related to IP.

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Xilinx Employee
Xilinx Employee

Adding soft IP Cores such as MicroBlaze Subsystems or DDR Controllers as part of the Update Region of a Tandem with Field Updates Design.

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Xilinx Employee
Xilinx Employee

In this article, we will discuss the concept behind output_delay.

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Xilinx Employee
Xilinx Employee

Vivado allows for a portion of the design to be synthesized Out-Of-Context (OOC).

The basic idea with an OOC flow is that a part of the design is synthesized by itself.

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Xilinx Employee
Xilinx Employee

For asynchronous clocks, there are four ways to write the constraints.

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Xilinx Employee
Xilinx Employee

Static Timing Analysis applies a concept called Time Borrowing for latch based designs.

This blog post explains time-borrowing, and is relevant to cases where your design has latches, and your timing report has time-borrowing.

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Xilinx Employee
Xilinx Employee

Sometimes, we might want a few signals to appear at more or less the same time time (i.e. the skew between these signals should not be beyond a certain limit).

A typical situation could be multiple bits of a bus, which should be arriving (almost) together.

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Xilinx Employee
Xilinx Employee

In general, if your design is passing simulation at a lower frequency but failing at a higher frequency, your first question should be whether the design is “timing clean” at the specified higher frequency.

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Xilinx Employee
Xilinx Employee

On Chip Variation leads to extreme pessimism in timing analysis.

A portion of this pessimism is recovered through what is called Clock Pessimism Reduction (CPR).

However, we often get queries from users saying that in their designs, instead of recovering a portion of the pessimism, the CPR section is actually doing the opposite, causing them to lose on timing (rather than gaining).

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Xilinx Employee
Xilinx Employee

This blog will focus on technical articles explaining how to achieve something specific with XLNX tools and solutions, or explaining some specific aspect of the tool behavior.

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