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Adaptable Advantage Blog - Page 2

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Adaptable Advantage Blog - Page 2

Xilinx Employee
Xilinx Employee

Let’s talk about data. The amount of data produced is exploding and our existing infrastructure is struggling to keep up. We are seeing industrial, vision, and healthcare equipment manufacturers getting out in front of this trend by working more closely with Xilinx. Why, you ask? Smart factory, surveillance, and hospital assets contribute heavily to the data explosion, and these companies and their customers want to figure out a way to manage data economically and securely. Xilinx’s heterogeneous and scalable SoCs address today’s and tomorrow’s needs!

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Xilinx Employee
Xilinx Employee

The DOCSIS Standard has evolved since its introduction in 1997 to provide increasing bandwidth for users. With advent of Distributed Access Architecture (DAA) the Remote PHY was introduced. Converged Inter-connect Network (CIN) connects the CCAP (Converged Cable Access Platform) core and multiple Remote PHYs providing higher bandwidth to users. This in turn permits operators to meet the demand of the evolving access market with the existing Hybrid fiber coaxial (HFC) infrastructure.

 

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Xilinx Employee
Xilinx Employee

Many of our solutions contain multiple processors, either hardcore processors like the Arm A9, A53 or R5, Softcores e.g. MicroBlaze, Arm Cortex M1/Cortex M3 or a combination of the two. 

When we implement a multiprocessor solution, typically we split the tasking between the available cores. Exploiting each core to maximise its performance attributes. For example using MicroBlaze or Cortex cores in the PL for dedicated real-time offloaded tasks while using hardcore application processors for higher level functions.

Of course, to correctly implement a multi-processor solution application, all the processors in the solution need to be able to communicate and share the available system resources safely and reliably. 

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Xilinx Employee
Xilinx Employee

Clocking is really one of the most fundamental aspects of FPGA / Programmable logic design, if we get it wrong then we are in a lot of trouble. Getting it wrong means our design may struggle to meet timing, or worse if we have not followed the clock guidelines regarding pin placement, clock usage, and routing correctly we may even struggle to implement the design. 

Of course this is before we even consider the more complex aspects of clocking which must be addressed such as working with multiple clock domains. 

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Xilinx Employee
Xilinx Employee

With security being a concern in most markets, why not take advantage of the built-in cryptographic hardware acceleration in the Zynq® UltraScale+™ MPSoCs and the Zynq UltraScale+ RFSoCs to accelerate all aspects of security?

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Xilinx Employee
Xilinx Employee

I use my Ultra96 a lot, for Hackster.IO projects, blogs and client prototyping if they are targeting a Xilinx MPSoC. I was therefore very happy to see the recent release of the Click Mezzanine which connects to the Ultra96 low speed connector and provides two MikroBUS sites

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Xilinx Employee
Xilinx Employee

Xilinx has introduced the Virtex® UltraScale+™ 56G PAM4 VCU129 FPGA evaluation kit to enable the design of a next-generation networking platform, bringing unparalleled adaptability and performance.

 

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Xilinx Employee
Xilinx Employee

Over the last few weeks, we have looked at how we can get MicroBlaze up and running using PetaLinux and connect it to the internet using Artix and Spartan-7 devices (P1, P2, P3 + P4).  

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Xilinx Employee
Xilinx Employee

Xilinx has introduced the Virtex UltraScale+ HBM VCU128 FPGA evaluation kit to enable the design of a compute acceleration platform, bringing unparalleled adaptability and performance.

 

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Xilinx Employee
Xilinx Employee

Many application domains that were bottlenecked in the past by insufficient compute power have been significantly advanced by the development of heterogeneous computing accelerators like the Xilinx® UltraScale™ devices, UltraScale+™ devices, and Versal™ ACAPs. Examples of popular heterogeneous compute-accelerated workloads in today's Data Centers are artificial intelligence, live video transcoding, and genomic analytics, to name just a few. Xilinx Virtex UltraScale+ HBM FPGAs provide unparalleled adaptability and compute acceleration to modern data-center workloads.

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Xilinx Employee
Xilinx Employee

Over the next two weeks I am speaking at three conferences (ESC Boston, FPGA Kongress & Embedded Online Spring Conference) on how we can implement Arm Cortex-M1 and Cortex-M3 solutions in our Xilinx FPGAs and SoCs under the Arm DesignStart FPGA program.

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Xilinx Employee
Xilinx Employee

Last week, we explored how we could update the design Zynq designs in the field and use MultiBoot to ensure there was a golden image should the update fail.

This week, we are going to examine how we can do the same when we use a standard FPGA. For this example, we are going to use a Artix-A7 100T device running a MicroBlaze design. The program executed by the MicroBlaze will be different depending upon the image.

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Xilinx Employee
Xilinx Employee

One of the beautiful things about FPGAs and heterogeneous SoC like the Zynq is that we can reprogram them in the field, often remotely.

This is great when we want to update algorithms, increase performance or fix a bug; however, what happens if in a remote update goes wrong?

The last thing we want to do is brick the system, if an update goes wrong. This is where MultiBoot comes into play. In the simplest manner, MultiBoot enables us to have multiple boot images in the configuration memory.

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Xilinx Employee
Xilinx Employee

A new collaboration between GuardKnox and Xilinx will enable the companies to work together in supplying a secure hardware architecture for connected and autonomous vehicles. Xilinx’s line of flexible and high-powered Field Programmable Gate Arrays (FPGAs) and Systems-on-a-Chip (SoCs) will be used in GuardKnox’s current product line of secure gateway domain controllers as well as in the company’s future secure products for securing body control modules and electric vehicle (EV) charging.

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Xilinx Employee
Xilinx Employee

Over the five plus years that this blog has now run, without a doubt some of the most popular blogs are on the XDAC / Sysmon functionality.

My last couple of blogs have been demonstrating how we can work with PetaLinux in our MicroBlaze systems (P1, P2, and P3).

In this blog I am going to show how we can get the XADC up and running such that we can monitor both the device supply voltages, die temperature and external signals. 

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Xilinx Employee
Xilinx Employee

Zynq® UltraScale+™ RFSoC ZCU111 evaluation kit, featuring the industry’s only single-chip adaptable radio platform, enables designers to jumpstart RF-class analog for high-performance RF applications. Zynq UltraScale RFSoC ZCU111 evaluation kits ship with the XM500 RF Balun add-on card to enable users to evaluate performance over a wide range of use cases including high band, low band, and differential configurations on distinct RF channels.

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Xilinx Employee
Xilinx Employee

A few weeks ago we looked at how we could create and run a Petalinux on the MicroBlaze (P1 & P2).

One of the key benefits of using an embedded OS such as PetaLinux is that it makes networking much simpler and we can connect to IoT frameworks such as IBM BlueMix, AdaFruit.io and AWS Services such as Lambda. Before we can work with these services we first need to ensure our MicroBlaze Petalinux build is correctly configured to support Ethernet.

 

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Xilinx Employee
Xilinx Employee

FlexEthernet (FlexE) is a new flexible Ethernet client interface standard defined by the OIF. FlexE specifies ways to support Ethernet MAC rates that don't correspond exactly to those in the IEEE's Ethernet specifications. FlexE supports a various Ethernet MAC rates such as 10G, 40G, and nx25G. Using FlexE enables network operators to decouple Ethernet rates on the client side from the actual physical interface via a new shim, packaging multiple Ethernet streams of 5, 10, 25 or even 100G into a higher rate interface. This enables network planners to integrate newer faster interfaces with existing interconnect and infrastructure. FlexE also allows the use of lower rate Ethernet PHYs to be used to send larger rate Ethernet MAC rates using bonding.

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Xilinx Employee
Xilinx Employee

In my recent audio processing project on Hackster.io on Hackster.io I created a simple High Level Synthesis (HLS) IP Block to which filtering, and effects could be added. To ensure this IP core would interface with the I2S TX and RX IP Cores from Xilinx I needed to create AXI Streaming interfaces on the HLS IP Block.

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Xilinx Employee
Xilinx Employee

A few weeks ago we looked at the Xilinx Deep Neural Network Development Kit and the DNNDK framework.

In this blog we are going to have a deep dive look at the element which is at the heart of the DNNDK — that is the Deep Learning Processor Unit, or the DPU, as it is commonly called.

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Xilinx Employee
Xilinx Employee

The CTO Office at Xilinx has been involved in the open source NetFPGA project since its inception. In particular, the Xilinx University Program has ensured that the NetFPGA family – featuring multiple generations of Xilinx FPGAs over the years – has been successfully used by academic researchers and teachers. Xilinx Labs has also had direct technical involvements, ranging from NetFPGA board and shell design on the hardware side, to P4→NetFPGA tool flow development on the software side. Xilinx is very happy to see this well-deserved award, which reflects the great impact of NetFPGA worldwide on research and teaching using FPGA-based software-defined networking.

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Xilinx Employee
Xilinx Employee

As previously noted in our PAM4 Technology at DesignCon - Part 1 blog, Xilinx partnered with four connector vendors to present six demonstrations showing what architects can look forward to using in their designs. Today, we're going to talk about demos with Samtec and TE.

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Xilinx Employee
Xilinx Employee

In last week’s blog, we implemented the Vivado design and proved the basic hardware design using BareMetal SW for a MicroBlaze on which we can run PetaLinux. In this blog we are going build the PetaLinux image and download it in to the Artix FPGA, so that we can use the PetaLinux Kernel.

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Xilinx Employee
Xilinx Employee

After nearly 40 years in the business, with customers writing 100s of millions of lines of application code running on billions of devices on earth and in space, the embedded industry’s leading software provider continues to deliver differentiated and disruptive offerings. The new platform, Helix Virtualization Platform, combines Wind River Linux and VxWorks under a common virtualization platform on the Xilinx Zynq UltraScale+ MPSoC.

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Xilinx Employee
Xilinx Employee

DesignCon 2019 has come and gone, and with it came a flurry of new interconnects targeting a variety of forward-looking serial technology. Xilinx partnered with four connector vendors to present six demonstrations showing what architects can look forward to using in their designs. From the near term 32G PCIe® style and emerging 58Gb/s PAM4 long reach interconnects to tomorrow’s 112G PAM4 topologies, Xilinx had SerDes technologies on display to fit everyone’s next generation wish list. In the following two weeks, we are going to release a series of Xilinx PAM4 technology demos from DesignCon. Stay tuned!

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Xilinx Employee
Xilinx Employee

The ability to add a high-level operating system to your SoC brings with it several advantages. It enables us to have several different applications running on it as they are multi-tasking and it greatly eases implementing network and communications. Of course, it is also used by a wide range of software developers, who are familiar with working with Linux helping accelerate the application development. In this blog and the next one we are going to look at how we can build a MicroBlaze system which runs Linux.

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Xilinx Employee
Xilinx Employee

The past few weeks have been very busy for the Xilinx Wired and Wireless Communications Group with demonstrations at both Mobile World Congress (MWC) and the Optical Fiber Communication Conference (OFC). The solutions covered all three major components of the 5G network infrastructure, including RAN, baseband acceleration, and the converged access network. For the latter component, which is key to a cost-effective 5G build out and services delivery, Xilinx presented its adaptable, intelligent vision for the design of converged xHaul gateways.

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Xilinx Employee
Xilinx Employee

The FreeRTOS kernel is a market leading real-time operating system for embedded systems. As embedded applications grow in complexity, there is a growing need for a lightweight kernel capable of task scheduling. Task scheduling enables developers to segment their embedded applications into independent threads of execution. This reduces the complexity of the design and improves CPU utilization for applications dealing with many asynchronous inputs and outputs.

Xilinx already provides support for FreeRTOS as part of the Xilinx Software Development Kit (XSDK). This integration makes developing FreeRTOS applications fast and easy for the Zynq® UltraScale+™ MPSoC, Zynq-7000 SoCs, and MicroBlaze™ soft-core microprocessor.

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Xilinx Employee
Xilinx Employee

NASA’s Opportunity Rover Mission came to an end on February 13, 2019 after exploring the surface of Mars for 15 earth years, even though the design was intended to last just 90 Martian days. NASA’s Mars Exploration Program is one of the most successful interplanetary exploration missions ever. We congratulate the team at Jet Propulsion Labs (JPL) and thank them for making Xilinx part of these historic missions. Though the Opportunity Rover is shutting down, the Curiosity Rover (aka MSL), also with Xilinx FPGAs on board, is still roaming the Martian surface. And as Curiosity continues to navigate, Xilinx is getting ready for future mission MARS2020!

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Xilinx Employee
Xilinx Employee

Xilinx announced Zynq® UltraScale+™ RFSoC Gen 2 and Gen 3 last week, which established Xilinx as an uncontested provider of monolithic, direct-RF, single-chip adaptable radio platforms, now with greater RF performance and scalability.

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