Hi,
I was wondering if it is possible to have ID width > 0 using Alveo U250/U280 boards. I am using the RTL development flow and I tried to increase the width of AxID ports directly in Verilog, but that led to the following failure:
ERROR: [VPL 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I2, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection
was removed due to the trimming of unused logic. The LUT cell name is: pfm_top_i/dynamic_region/memory_subsystem/inst/interconnect/interconnect_ddr4_mem00/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/m_vector_i[0]_i_1.
